Please verify to make sure this information here is correct.

The external hardware of the keyboard's Reset key is down. It causes to pull Reset' line low. NMOS 6502 MPU waits the current 6502 instruction like LDA $xxxx to be completed. After four clock cycles of LDA $xxxx is spent. NMOS 6502 MPU is frozen for a long time. You release Reset key. The Reset key pulls Reset' line high again. NMOS 6502 MPU begins the 7 clock cycle Reset' sequence. It restarts to start main program in warm boot.

Correct?

Reset' line, NMI' line, and IRQ' line are low at the same time. Reset' line is pulled high while NMI' line and IRQ' line are still low. Seven clock cycle Reset' sequence begins until Reset' low vector byte and high vector byte are loaded into Program Counter register.

The first 6502 instruction will not be executed while seven clock cycle NMI' sequence begins. Reset' low vector byte, Reset' high vector, and Processor Status are pushed into stack. NMI' ISR is in process while NMI' line is pulled high again.

NMI' ISR is complete. RTI pulled Processor Status, Reset' low vector, and Reset' high vector out of stack. The Reset' low vector and Reset' high vector are restored back to Program Counter. The first instruction of the boot-up main program starts.

The main program can use CLI to enable IRQ Disable Flag. Seven clock cycle IRQ' sequence starts until IRQ' line is pulled high again. ISR is complete and main program is resumed back to normal.

The main program is still running while it waits for next NMI' or IRQ' interrupts.

Correct?

Do not connect the reset button directly to the RST\ line. Make sure you have de-bouncing hardware. The CMOS 6502 has a Schmitt-trigger RST\ input, so a simple RC will work; but the hysteresis seems to be rather small, so put the capacitor immediately from the RST\ pin to the closest ground pin, with the leads as short as possible, so it won't be vulnerable to electrical noises coupled in which can cause problems. (Been there, done that.)

As for the others, remember that the processor will come out of reset with the I flag set, so it will ignore the IRQ\ input until you clear the I flag. Also, if the NMI\ falls while RST\ is low, I am sure the processor will not "notice" it and respond. It is kind of irrelevant though, as the interrupt sources typically will also be reset when RST\ is taken low, and will have to be set up by the software.

Yes, I do understand. I do know Reset', NMI' and IRQ' start 7 clock cycle sequence and sets IRQ Disable Flag to "1". I am aware that Reset' interrupt ignores low NMI' line and low IRQ' line during Reset' 7 clock cycle sequence.

One question is still unanswered.

For example, low Reset' vector and high Reset' vector from $FFFA and $FFFB are loaded into Program Counter register. Program Counter register looks like $F800. $F800 is the main program to initialize A, X, Y, and stack register before normal program starts.

I am trying to ask. Reset' 7 clock cycle sequence is complete and NMI' 7 clock cycle sequence starts at 8th clock cycle through 14th clock cycle. Reset' vector: $F800 are pushed into stack during low NMI' line because first instruction at $F800 did not start or execute yet. After 15th clock cycle, NMI' ISR is complete and returns back to $F800 and the first instruction at $F800 resumes.

If NMI' line is not low yet after 10,000 clock cycles are spent since Reset', NMI' ISR will not occur while main program at $F800 is running since 8th clock cycle through 10,000 clock cycles.

Is my explanation clear?

Again, NMI\ is not level-sensitive. It is edge-sensitive. If the line was low during reset, and it is still low when the reset line comes up and while the processor goes through the reset sequence, it will not see a high-to-low transition, so it will not respond to NMI\ being low.

What I don't know is how many cycles the processor would have to have progressed through the reset sequence before it will detect a high-to-low transition on NMI\. Maybe it will only accept it in the last 20ns of the last cycle, and anything before that would be ignored. It would be much easier to experiment with the CMOS 6502 since you can stop the clock, single-cycle it manually with $2 in parts in a home-made breadboard and look at every address, data, and control line with a logic probe which could be as simple as an LED and 1K resistor. The NMOS 6502 cannot be stopped however. This experiment will only work with the CMOS 6502.


If indeed the processor will even see the NMI\ high-to-low transition before first instruction, the 15th cycle will be the beginning of the ISR. Even if the ISR only consists of an RTI instruction and does nothing else, it will not get back to the main program until at least cycle 21.

There is no need to initialize A, X, and Y, as each part of the program will do whatever initializing it needs to do, if any, since it cannot assume the initial values are anything meaningful unless you are passing parameters via these registers. The things the reset routine normally does are:

CLD (not necessary on CMOS 6502)
Initialize the stack pointer
Set up the I/O
Set up interrupt sources
Initialize system flags, variables, arrays, etc. in RAM
etc.

Much of this can be done in a higher-level language after only a few instructions in assembly

Yes, it does make sense. Let me make a list of clock cycle sequence below according to my figure. Please read my comments below clock cycle sequence.

Clock RST' NMI'
X High Low
X High Low
X Low Low Need least 2 clock cycle to respond Reset'
X Low Low
1 High Low RST' 7 Clock Cycle Sequence
2 High Low
3 High Low
4 High Low
5 High Low
6 High High** RST' Low Vector loaded into Low PC
7 High High** RST' High Vector loaded into High PC
8 High Low NMI' 7 Clock Cycle Sequence
9 High Low
10 High Low RST' Low Vector pushed into stack
11 High Low RST' High Vector pushed into stack
12 High Low RST' P pushed into stack
13 High Low NMI' Low Vector loaded into Low PC
14 High Low NMI' High Vector loaded into High PC
15 High Low NMI' ISR Starts
...
...
...
50 High High
51 High High NMI' ISR Ends prior RTI
52 High High RTI executes
53 High High
54 High High
55 High High RST' P pulled from stack
56 High High RST' Low Vector pulled out from stack
57 High High RST' High Vector pulled out from stack
58 High High Start-up -- Main Program Starts
52 High High
...
...
...

Do you see what I mean? Unfortunately, we agree that NMI' line is not accurate to be low-to-high and then high-to-low during Reset' 7 clock cycle sequence.

It may be helpful to prove if it is true. Unfortunately, I like your advice. I don't have Logic Analyzer. I have no way to stop CMOS 6502 MPU using STP instruction. I am sure that address bus and data bus are helpful to see data.

It would be nice when you do your experiment to see if you have time.

If I hit Reset key after main program already started and is running, RST' 7 clock cycle sequence needs to wait until current instruction is complete before Reset sequence begins. (Right?)

Do you believe that Sync line (Sync's pin from 6502 MPU chip) should go High during first clock cycle of RST', NMI', and IRQ's 7 clock cycle sequence. Then Sync line goes low on 2nd through 7th clock cycle. It does the same to all instructions during first cycle. Sync helps to identify instructions, RST', NMI', and IRQ'. It is helpful to step-in debugging using Logic Analyzer.