kc5tja wrote:
Hello again. Just poking in to contribute here, since this is more or less relevant to my FPGA activities right now. What isn't made clear here is what the DMA controller will be used for. Is this intended for use with a generic hardware interface of some kind, sort of like the DMA channels on the PC/XT and ISA buses? Or, will this entail a complete bus master implementation? The answer will determine how to go about building such a controller.
Howdy, Samuel. In my area of interest, I would entertain the idea of it acting as a bus master. My specific application would be to enhance SCSI I/O throughput. I'm currently simulating the effect of a DMA controller by having the MPU manipulate the 53C94's /DACK input and polling the chip's DREQ output. Although this "DMA simulation" adds cycles to the basic I/O loop, it still runs pretty fast—nearly 500KB/second on burst transfers of 48KB. However, a DMA controller that can act as a bus master could easily achieve 6-8 times that performance, nearly equal to that of the SCSI bus' throughput in synchronous mode.
At one time I had given some thought to the idea of rigging up a 65C02 to act as a DMA controller, with the 'C94's DREQ output tied to the 'C02's IRQB input and the latter sitting on a WAI instruction with IRQs disabled, which results in a one cycle response time to the 'C94 saying it has, or is ready for, data. I abandoned the idea after doing some cycle counts—it would have been, at best, twice as fast as the current method, being limited by the 'C02's ability to read and write memory.
In my opinion, any DMA controller intended to run with the '816 would have to effectively transfer a byte per 2-3 clock cycles to be worth the bother. The throughput with such a device could reach 6-10 MB/second, certainly nothing to sneeze at. I suppose with suitably fast silicon, a byte per clock cycle would be feasible, something that I would be very enthusiastic about. 
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