Quote:
Is PHI-IN normally held high or low in single-step/clock-stopping setups?
Normally high. WDC's are the only ones that can be stopped indefinitely with phase 0 (and 2) low, and only the high lets you probe the buses and see what you probably want to see. All the CMOS 6502's can be stopped indefinitely with phase 0 high, regardless of brand. NMOS ones cannot be stopped in either one without losing information.
Quote:
Also, which edge starts the cycle: rising or falling? Because the WDC datasheet shows the falling edge first, I assume that's the start.
Right. down, then up.