Nice to hear about the progress with troubleshooting. Regarding your post from yesterday, ....
Marta wrote:
The diagram has a magic symbol, red marked in the picture, that I wonder what it is.
I'm guessing -- and with WDC doc that's not unusual -- but I suspect the odd symbol simply denotes that that segment of the bus is bidirectional.
Quote:
My chips are old Sanyo, are there any known differences with the TSMC chips?
Probably the old Sanyo electrical and timing specs weren't quite up to modern TSMC standards, but with a 1 MHz project which loads the bus only lightly (ie, all or mostly MOS devices) odds are you'll be OK. Slower timing can even be a benefit in some ways! Also, from the Wikipedia article I gather that Sanyo 816's (unlike the modern WDC product) were not fully static. But I can't see why that'd affect your troubleshooting so far.
Quote:
The setup is now back as it was from the beginning
Rather than asking us to mentally edit and rewind, perhaps it'd be better to provide a fresh description. Furthermore, I think we would benefit from a full (or at least fuller)
schematic.
Some additional photos may prove helpful, too.
Quote:
It would be interestning to run the obstructing instruction wiith a logic analyser. Unfortunately I have no access to any...
The scope can be as good (or better)! Admittedly, with an analog scope only a small time slice can be viewed. Also you need the cycles in question to happen repeatedly. But that's easy to do if the machine is capable of executing a loop. And if not you can apply a pulse train to /RESET, using an EPROM whose reset vector points directly to the test snippet! Or have an EPROM which is entirely filled with identical successive iterations of the snippet.
BTW and FWIW, I think it's best to assume that other things may also broken, not just JSR (ABS,X) instruction.
-- Jeff
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
Login
Register
FAQ
Search
