As noted earlier, there's more than one "right answer" to the question. Here again is the "classic" schematic -- the arrangement which uses a pair of NAND gates to generate qualified /Read and /Write signals from Phi2 and the CPU's R/W output. I added the Truth Table for typical RAMs.
Attachment:
basic 816 glue_.png [ 13.06 KiB | Viewed 431 times ]
Now here's a schematic which, by comparison, has both advantages and disadvantages. Therefore it's reasonable to make your choice according to prevailing priorities and circumstances.
Attachment:
basic 816 glue v2.png [ 13.31 KiB | Viewed 431 times ]
The classic circuit requires more gates, but it may be a better choice if you're keen to run an old-ish RAM at the highest possible speed. /CE is what "wakes up" the chip and moves it from "power-down" to "selected," and the classic circuit allows /CE to go true ASAP. Then later when Phi2 rises we get the actual Read or Write. These four modes are shown in the Truth Table (and the "classic" version uses all four modes)
The new circuit is simpler but the RAM remains in "power-down" until Phi2 rises; then it transitions directly into either Read or Write. (The "selected" mode never occurs.) The lack of an advance wake-up results in a performance penalty which you may or may not deem significant.
It may seem odd that /OE is grounded; however, in the Truth Table you'll see that the state of /OE doesn't matter (it's a "don't care") if /WE is low. /WE and /CE alone are sufficient to select the three modes we need: power-down, read and write.
( Whether you do or don't choose the classic circuit is a general decision -- it has no specific bearing on the use of the '816 as opposed to '02 or 'C02. )
-- Jeff
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
Login
Register
FAQ
Search
Just got up, heading to work. To be continued!
