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 Post subject: Re: Schematic Confusion
PostPosted: Thu Nov 29, 2018 5:34 pm 
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Joined: Thu May 14, 2015 9:20 pm
Posts: 155
Location: UK
Just saying that you should be careful about your assumptions...

Mark


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 Post subject: Re: Schematic Confusion
PostPosted: Thu Nov 29, 2018 5:40 pm 
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Joined: Thu Dec 11, 2008 1:28 pm
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It's one of the facets of teaching, I think, that there are some things worth omitting. (Because it's one of the facets of learning that you can't just upload every true fact and find that you understand.)

(I don't wish to be hostile, of course. We all have our hard-won knowledge and it feels good to share it. But I think it's good to consider which thread is getting the benefit of our wisdom before hitting Submit. More often than not, a comment which might be off-topic or out of scope in one thread would be a great starter for a new thread.)


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 Post subject: Re: Schematic Confusion
PostPosted: Mon Dec 03, 2018 6:16 pm 
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Here, I made the circuit of the clock generator using logic gates. Is this an accurate diagram?


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 Post subject: Re: Schematic Confusion
PostPosted: Tue Dec 04, 2018 5:51 pm 
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Hmm, sorry to say, I don't much like that - it looks like you've put AND gates in for the final drivers.

From a logic perspective, aside from tristate drivers, I think you can just count all pullups as pullups. An inverting superbuffer is drawn as an inverter, a non-inverting superbuffer is drawn as a buffer. I'm not aware of any special symbol for a superbuffer.

These resources might be of interest:

Chapter 1 of Mead & Conway, the classic textbook on VLSI:
http://ai.eecs.umich.edu/people/conway/ ... V1.Ch1.pdf

A short slide-deck on inverters and buffers in NMOS and other technologies:
http://xa.yimg.com/kq/groups/21151486/4 ... teering_lo
gic.pdf


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