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jmthompson
 Post subject: Re: WDC Errata
PostPosted: Fri Mar 30, 2018 2:59 pm 
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Rob Finch wrote:
On the W65C816S data sheet dated March 2000, page 16 section 2.6 talking about interrupts states that the processor only saves the program counter high, low, and status register. But later in the document in a table it shows the processor also saving the program bank register during interrupt. So it seems a little inconsistent.


It depends on whether or not the processor is in emulation mode. In emulation mode (E=1) it will not save the PBR, but in native mode (E=0) it does.
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Dr Jefyll
 Post subject: Re: WDC Errata
PostPosted: Fri Mar 30, 2018 3:24 pm 
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Rob Finch wrote:
it seems a little inconsistent.
Sounds as if they merely failed to make the context clear. If the CPU is in Emulation Mode an interrupt will only push 3 bytes. But in Native Mode it'll be 4 bytes because the program bank register is also saved.

Edit: doh! I overlooked the post where jmthompson already mentioned this

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Alarm Siren
 Post subject: Re: WDC Errata
PostPosted: Fri Mar 30, 2018 9:58 pm 
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Perhaps the first reference is for when its working in emulation mode, the latter native mode?

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