BigEd wrote:
For 9+8 in decimal mode, I see ~C34 is low, so there is indeed a half carry. It's true that DC34 remains low, and so no carry is forced, but you get the natural carry from the binary adder. DC34 is a force carry signal, not a substitute carry in.
I can't help you much with the details of the diagram - I'd be fairly confident it's correct, but I'd probably refer to Balazs' schematic for this.
Hi Ed,
Do you have more knowledge by understanding 6502 microprocessor, but your knowledge is very limited about NMOS transistors schematic? Balazs is very good with electronic engineering to do reverse engineering of 6502 microprocessor.
Look at thousands of transistors and 6502 simulator is very difficult to understand because most transistors have labels with numbers only, but no names. I assume he is uncertain to obtain more information because he is unable to obtain an original 6502D schematic from the designer, but he is supposed to have 6502C.
Are you certain 6502 simulator is 6502D, but not 6502C?
I am more interested to translate thousands of transistors into hundreds of logic gates with symbols like AND, OR, NOT, etc so that big diagram can be reduced to half size.
Take care,
Bryan Parkoff