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 Post subject: Re: Visual 6502 Question
PostPosted: Tue Mar 26, 2013 7:10 pm 
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For 9+8 in decimal mode, I see ~C34 is low, so there is indeed a half carry. It's true that DC34 remains low, and so no carry is forced, but you get the natural carry from the binary adder. DC34 is a force carry signal, not a substitute carry in.

I can't help you much with the details of the diagram - I'd be fairly confident it's correct, but I'd probably refer to Balazs' schematic for this.

Cheers
Ed


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 Post subject: Re: Visual 6502 Question
PostPosted: Wed Mar 27, 2013 10:54 pm 
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BigEd wrote:
For 9+8 in decimal mode, I see ~C34 is low, so there is indeed a half carry. It's true that DC34 remains low, and so no carry is forced, but you get the natural carry from the binary adder. DC34 is a force carry signal, not a substitute carry in.

I can't help you much with the details of the diagram - I'd be fairly confident it's correct, but I'd probably refer to Balazs' schematic for this.


Hi Ed,

Do you have more knowledge by understanding 6502 microprocessor, but your knowledge is very limited about NMOS transistors schematic? Balazs is very good with electronic engineering to do reverse engineering of 6502 microprocessor.

Look at thousands of transistors and 6502 simulator is very difficult to understand because most transistors have labels with numbers only, but no names. I assume he is uncertain to obtain more information because he is unable to obtain an original 6502D schematic from the designer, but he is supposed to have 6502C.

Are you certain 6502 simulator is 6502D, but not 6502C?

I am more interested to translate thousands of transistors into hundreds of logic gates with symbols like AND, OR, NOT, etc so that big diagram can be reduced to half size.

Take care,
Bryan Parkoff


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 Post subject: Re: Visual 6502 Question
PostPosted: Fri Mar 29, 2013 9:24 am 
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Hi Bryan
no, I wouldn't say my knowledge is very limited, but I don't always have the energy to answer all questions! Hanson's diagram is surely very good but it is a diagram, not a schematic. If it has a few gates drawn on that's fine, and you might like to understand exactly what's going on, but I don't want to try. More interesting of course are the more detailed results by Balazs - but it is incomplete and it does have errors. Finally, the best data we have is visual6502. It's less accessible but it is known to simulate correctly and indeed in emulation on FPGA has run VCS software. (It's also true that other people are looking at layout data and trying to build models)

I wish you well, and will answer any of your questions which I find interesting and easy enough to answer, but I may not always give you what you want - maybe someone else can help, or you can figure out the answer yourself.

Cheers
Ed


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