For the purposes of this discussion, imagine you are in circa 1980, and that the 65C02, 65816, and all the other subsequent extensions are variants do not exist. The 6502 has been a smashing success, but its time to give it a backwards-compatible upgrade. How would you upgrade it? What modes, instructions, extra pins, etc would you give it? 16 bit? 32 bit? hybrid? Stack? Movable direct page? more registers? Why?

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Here are some past related discussions that come to mind:
65VM02
6502 redundant, missed, and suggested features
Instructions that I missed
65Org16 - extending the instruction set
Improving the 6502, some ideas
"Homebuilt" 6502 cpu's

I have links to various commercial attempts and other white papers at http://wilsonminesco.com/links.html#65fam .

Edit: I am reminded that Ed has an excellent collection of links to relevant discussions, at viewtopic.php?f=1&t=4216, the topic, "Index of threads for improved 6502 and derived architectures."

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What's an additional VIA among friends, anyhow?

The basic 65C02 was an excellent start along those lines. In particular, I'd take BRA, PHX/Y, PLX/Y, STZ, and the new zero-page-indirect and pre-indexed-indirect addressing modes. The proper initialisation of D and I flags, which was introduced in the 65C02, is also important, and I'd also take the "long relative branch" instructions from the 65816.

In 1980, a larger address space is not yet an essential feature; 64Kbit DRAMs were not available at usable prices until 1984. But seamless access to the full 16-bit address space is the big missing feature of the 6502, so I'd also look into the least obtrusive ways to extend the index registers to 16 bits. The additional mode bits of the 65816 are not the right choice, I fear, but there may be room for extra instructions that treat the indexes as 16-bit instead of 8-bit; the existing instructions would ignore and/or zero the high-order bits. An addressing mode which directly used the value of either index register as an address would then make sense, as well as one which could apply a signed constant offset to that address.

The hardware costs of the above features should not be prohibitive within the 6502's market. This is important, and is why I haven't included a multiply or divide instruction, nor a barrel shifter. Those are features which only become cost-effective in the *late* 1980s.

There are a few features of the 6809 that I like very much: Two stacks, pre-decrement and post-increment addressing, indirect+offset addressing, DP registers, multi-register push/pop, and more. These more complex instructions necessarily increase worst-case interrupt latency, but that's a trade-off I'd be willing to make for a higher functioning ISA. Oh, and do it at the 6502 price point, not the 6809 price point. Yes... give me all those extra transistors but I don't want to pay for them

I don't think I'd want to take on the 68000 as machine architectures got wider and memory got larger. I like the design-for-purpose 68000 ISA far more than the evolved-over-time 8086... even though the '86 won in the end, it's a pretty ugly ISA.

It would be useful, in the era I think, to support more than 64KB, but I think the way to do that would be via some sort of extended address mechanism as opposed to widening registers beyond 16-bits. My preference would be to keep software compatibility with the 6502, and I'm not really a fan of fundamental operating mode switches, even though they're not uncommon.

Not a huge deal, but I'd like a "swap nibble" instruction... I don't know how many times I've had to do that the long way.

Daryl

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I really like:
From the 'c02: phx, phy, plx, ply, stz, bra, ina, dea; (zp) addressing
From the 'c816: xba, txy, tyx, brl; d,s & (d,s),y addressing
From the 6800: bsr, add, sub
From the 6809: auto-increment and auto-decrement indexed addressing

(How would all of these enhancements fit into a one-byte op-code? Quite easily if we had 10-bit bytes! Seriously, I think 8-bit bytes are just too constrictive, and I personally blame them for most of the growing pains experienced by the designs of the 70s, including the 6xxx families. A 10-bit byte version of the 65c02 with 1MB of 10-bit address space would have charmed the heck out me back in the day ... or even now!)

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With a 10-bit byte, you could have the entire 6309 instruction set without prefix codes.

It's an interesting date, because by 1980 you are on the cusp of needing to access more memory, and it's difficult to see a clean way to do it inside the CPU.

I'd go with Mike's wish-lists from the contemporary machines, but I'd add multiplication, and a second stack (as sark02 notes.)

I think by 1980 you'd be looking at support for compiled code. It might be time to get past that one-page stack.

Mike's wish would yield a one-page stack area of 1024 10-bit bytes!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I think, it would need to be cost effective (meaning keeping it's low cost) and you would also need to keep development time short. As to be successful, you would want to sell at the same, or very nearly the same price point as the existing NMOS 6502 price. Hence the improvements should not be too hard to implement.

So having some extra registers may help, such as a high address byte for the "zero" page, the same for the stack. Maybe also for the index registers.

I would keep the device in the same package (40 pin DIL/DIP) but add tri-state buffers on the output pins, controlled by an input pin, so that it's easier for other devices to take control of the busses.

If possible, some additional easy to implement instructions would be added, like the "swap nibble" instruction that Daryl mentioned. And some of the extra instructions that the 65C02 added, such as phx, phy, plx, ply. How many, very much depends on the costs...

Mark

I haven't said much except give links so far, because we have discussed this at length so many times; but one thing I will add is that although most of what everyone brings up is already in the 65816, I wish it were in the next package size up so the high address lines aren't multiplexed. There was a 48-pin DIP which would be adequate, barely, and a 68-pin DIP and PLCC and PQFP. The 68-pin DIP was huge though, not just longer, but .9" wide. I have a VME-bus board here with a 68K processor in a 68-pin DIP, and they put a lot of ICs under the processor.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

We'd be straying a little way from the 6502's usual values, but
- if we had separate i/o space
- and a separate space for vectors and boot code
- we could have multiplexed address bus suitable for DRAM, for data accesses
- and support for full 64k-sized banks too
and all (perhaps) without going over 40 pins. (40 pin DIP is really important for cost, and if the 6502 successor isn't cheap, that would be a problem.)

I heard years ago that testing was a major factor in the cost, and that more pins added a lot to the testing (and maybe to the failure rate). I'm not too concerned about that now though. Just for reference, I looked up Mouser's price for a PIC18F26K42-I/MX microcontroller in a 48-pin TQFP, and it's $1.78 in qty 1. The PIC24EP64GP206-I/PT in a 64-pin TQFP is $2.98 in qty 1. I'm not sure anyone is making DIP leadframes in more than 40 pins anymore.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Yes, moving away from DIP and the rise of surface mount were important developments - but I think in 1980 very much in the future? The Transputer was a PGA device, quite a good package for through-hole technology, but just a little later.

Having said that, it seems TI had a PLCC offering in the late 70s.

I have often thought that 12-bit bytes would have been very efficient, I never considered using a metric byte per your suggestion.

A 12-bit byte would allow you to easily mix x1, x2 and x4 bit wide memory chips, although if the metric byte were the standard I suppose we'd see 5-bit parts rather than 4-bit wide parts so that might not have been an issue.

A 12-bit byte would also fit three full nibbles.