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PostPosted: Tue Apr 15, 2014 12:29 pm 
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I am told that Visual 6502 Simulator has eight iterators to process all transistors and nodes. If one of these transistors is turned on, then npwr in node connected to c1 is copied to another node connected in c2 through "if then" statement. What is 'bb' for found in transdefs array?

I can't find which functions they have iterators. If I am right, both npwr and ngnd are set to 1 before if NPN's gate of transistor is set to npwr, then ngnd is inverted to set to 0.

Who wrote Visual 6502's java scripts?

Take care,
Bryan Parkoff


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PostPosted: Tue Apr 15, 2014 3:18 pm 
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Hi Bryan
It was Brian and Barry Silverman who wrote the simulation engine, I think. Greg James did the deprocessing and polygon capture and possibly some of the JavaScript too - all three were involved in the debugging and bringup. I did some of the later work in refining and extending the user interface, and at that time we also improved the performance.

I'm not aware of there being eight iterators. The simulation engine is iterative - it loops until convergence, for some maximum number of iterations. I think the worst case is in the region of 20-30 iterations for a clock phase, depending on what the chip is doing.

I know the simulation engine needed some fine-tuning to ensure convergence - the algorithm is inherited from the 4004 model which is written in Logo. I think perhaps there are fewer difficult circuits in the 4004. There was more fine-tuning needed when we tackled the 6800, which has enhancement-mode pullups and some different transistor circuits.

The 'bb' data is the bounding box data, used to highlight a transistor when you click on it. We might have thought at one point to use the bounding box as a proxy for drive strength, but we never did. (It wouldn't model serpentine transistors very well.)

Cheers
Ed


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PostPosted: Tue Apr 15, 2014 9:35 pm 
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Hi Ed,
BigEd wrote:
It was Brian and Barry Silverman who wrote the simulation engine, I think. Greg James did the deprocessing and polygon capture and possibly some of the JavaScript too - all three were involved in the debugging and bringup. I did some of the later work in refining and extending the user interface, and at that time we also improved the performance.
I discussed last year. There are many ways to improve the performance so that logical data such as AND, OR, NOT, etc can be used to replace "IF THEN" statement due to avoided branch misprediction. I have not written my code yet, but it is on my draft.
BigEd wrote:
I'm not aware of there being eight iterators. The simulation engine is iterative - it loops until convergence, for some maximum number of iterations. I think the worst case is in the region of 20-30 iterations for a clock phase, depending on what the chip is doing.
First iterations will read all 3,510 transistors and update 1,704 nodes. Sometimes, second iteration or more are needed in order to update some nodes before next half cycle repeats the loop.
BigEd wrote:
I know the simulation engine needed some fine-tuning to ensure convergence - the algorithm is inherited from the 4004 model which is written in Logo. I think perhaps there are fewer difficult circuits in the 4004. There was more fine-tuning needed when we tackled the 6800, which has enhancement-mode pullups and some different transistor circuits.

The 'bb' data is the bounding box data, used to highlight a transistor when you click on it. We might have thought at one point to use the bounding box as a proxy for drive strength, but we never did. (It wouldn't model serpentine transistors very well.)
It will be nice to add second version of Visual 6502 to the Visual 6502's website in JavaScript language. The Visual 6502 is filled with the number of transistor's symbols in perfect alignment. For example, dark red pull-up transistor (depletion mode) will be light red when the power is turned on prior reseting MPU 6502. The dark red pull-up and green pull-down transistors (enhancement mode) will be light red and light green when the gate is set high and back to dark red and dark green transistor again when the gate is set low.

You have seen my drawing schematic. The image will look nicer with full details. No more original photo of MPU 6502. The number of transistor's symbol will do better.

What do you think? Will the designers of Visual 6502 accept my project and they add it to their website in the future?

Take care,
Bryan Parkoff


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PostPosted: Wed Apr 16, 2014 5:48 am 
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Hi Bryan
I think your best bet will be to make a fork of visual6502 and get your idea on display that way. If you are hoping to get your idea into the officially published version then I think it would need to be added as an additional display mode, not as a replacement. You may have seen that there's a fork of visual6502 which displays the NES chip - see http://www.qmtpro.com/~nes/chipimages/visual2a03/ - the point of visual6502 being open source is that anyone can fork it and put their own ideas on display. (It's relatively easy to do the forking and the hosting on github - all for free.)

On the subject of simulation convergence, in the default simulation that visual6502 runs, the first half of cycle 23 - the T2 state of RTS - which is half-cycle 47, visual6502 takes 19 iterations to converge. The last few nodes to settle are in the high bits of the ALU. You can set the variable ctrace to true, and also modify the function recalcNodeList to get more information about what's happening.

Of course if you have your own simulation model, it will have different convergence characteristics.

Please add a picture or link to your schematic in this thread so we can refer to it.

Thanks
Ed


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PostPosted: Mon Oct 13, 2014 8:56 pm 
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We've just posted a different version of the simulator in Python. Node names and numbers match the javascript version:
https://github.com/gregjames/Sim2600


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