That page references Whetstone, which is a floating-point benchmark.

Since the 6502 has no FPU and must perform all floating-point operations in software, the quoted figure of 3 milliMIPS for Whetstone does not seem unreasonable.

Toshi

Up until 2007, my office file and print server was running the same MPU. I replaced it only because a piece of silicon on the motherboard went south. Now the server has a dual core Opteron.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Studies show that 98% of the instructions used by VAX implementations are of the reduced variety (these same studies informed the DEC Alpha AXP engineering team when they designed the instruction set) -- e.g., compilers generally don't produce code utilizing the extended addressing modes, or the complex functionality. Therefore, my comparison is more appropriate than you might think.

You are also assuming that one 32-bit variable in zero-page corresponds to one 32-bit register in VAX, which is only part of the story. Code compiled for the 6502 would of course exploit whatever unique features the 6502 instruction set provides. I know it's not much, but history bears me out on this.

Comparing an Intel 8088 against a 6502 at half the clock rate shows the 6502 snows the 8088, despite using 16-bit wide instructions. Why is this? Because code written for the 6502 was tailored for the 6502, exploiting its unique behavioral characteristics to maximum effect.

I'm not arguing for the sake of arguing here -- I am simply pointing out that your assessment of relative performance of the two architectures tends towards the overly simplistic view. It's the same mistake taken by the 68000-versus-65816 folks. Yes, the 68000 is somewhat faster than the 65816, but not by much, as both practical experience (an Apple IIgs at 2.8MHz updates a 16-color display every bit as fast as the Mac Classic at 8MHz can update a monochrome display, which says a LOT) and by benchmarks.

oops, my mistake. The page mentions VAX MIPS which are fixed-point, but for the 6502 only tabulates MWIPS, which as you say are floating point. I googled for Dhrystone rating of 6502 but didn't find anything. I suppose compiling Dhrystone for 6502 with ca65 or lcc (or for 65816 with snes-sdk) would be the thing to do.





Interesting - similar conclusions! And there are several 65816 projects capable of 12MHz or better - our 65816-in-BBC-micro project among them. Edit: so we can all have a VAX each!

I found a link which indicates the 6502 at 1MHz gets 32 Dhrystone 2.1 per second (you'll need to scroll way down on the page to see the table), or 36 Dhrystone 1.1 per second.

We can thus ball-park the 65816's performance at 20MHz. If we execute the same 6502 binary as-is, we should receive a benchmark of 640 Dhry/s. Taking a conservative estimate of 1.7 factor performance gain by switching to a compiler with the same overall strategy but which emits 65816-native instructions in 16-bit mode, we can reasonably expect a performance of 1088 dhry/s. With more aggressive optimizations and compilation techniques, you can probably pull higher figures.

Update Strange -- according to the Apple II FAQ, the 65816 @ 2.8MHz exhibits a 236 Dhry(1.1)/s performance. This is some 6.5x better than a 1MHz 6502. It seems my conservative estimate above may be too small in the general case; it looks like the real scaling factor is closer to 2.3. However, the 65816 accelerators discussed in the FAQ do not scale well; perhaps because they're operating with a caching mechanism over the 1MHz Apple II bus? It would seem to me that a 20MHz 65816 should be capable of 1685, yet the FAQ implies smaller figures. In either case, though, the combination of 65816 and C yields much slower results than a 68000 and C. With an estimated 1685 dhry/s for a 20MHz 65816 and an estimated 2848 for a 20MHz 68000 (based on the largest 12.5MHz 68000 rating), the 65816 seems about 1.7 times slower. This near factor of two leads me to believe it's because of 16-bit vs. 32-bit operations. But, we knew this was the case right from the start.

If anyone has a working C compiler for the 65816 target, I'd be very interested in seeing what confirmation or refutation comes from running Dhrystone benchmark.

I recognize that Dhrystone has been obsoleted by more relevant benchmarks within the last decade or two. Nonetheless, Dhrystone remains useful for ballparking one CPU/compiler combination against another, at least for integer performance.

I know you guys were talking about Whetstone and Dhrystone benchmarks, but I was perusing my 2nd favorite forum and viewed this interesting piece: Link here, related to Cray in FPGA!: http://cde.cerosmedia.com/1N4cc1a89f283 ... de/page/36

Finished reading. He started the project, but it is a WIP... Still, a CRAY in a FPGA?! That's cool!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502