As an aside: the new RP2350 has some serious bugs in the IO relating to accidental latchup. Some of this is documented, some is still being investigated, but it looks rather as if new silicon is required. It seems an external IP supplier didn't get the IO pins quite right...

Reference: RP2350-E9

Summary: Increased leakage current on Bank 0 GPIO when pad input is enabled

Affects: RP2350 A2

Description:

For GPIO pads 0 through 47:
Increased leakage current when Bank 0 GPIO pads are configured as inputs and the pad is somewhere between VIL and VIH (the undefined logic region).
When the pad is set as an input (input enable is enabled and output enable is disabled) and the voltage on the pad is within the undefined logic region, the leakage current exceeds the standard specified IIN leakage level. During this condition the pad can source current (the exact amount is dependent on the chip itself and the exact pad voltage, but typically around 120μA). This leakage will hold the pad at around 2.2 V as that is the effective source voltage of the leakage, and can only be overcome with a suitably low impedance driver / pull.
Note that the pad pull-down (if enabled) is significantly weaker than the leakage current in this state and therefore is not strong enough to pull the pad voltage low.
Driving / pulling the pad input low with a low impedance source of 8.2 kΩ or less will overcome the erroneous leakage and drive the voltage below the level where the leakage current occurrs, so in this case if the pad is driven / pulled low it will stay low.
The erroneous leakage only occurs (and continues to occur) when the pad input enable is enabled; disabling the input enable will reset (remove) the leakage.
The pad pull-up still works. If enabled it will pull the pad to IOVDD as it will pull the input voltage out of the problematic range.
...
In detail, this issue presents under the following conditions, for any GPIO 0 through 47:
1. The voltage on the pad is in the undefined logic region.
2. Input buffer is enabled in GPIO0.IE
3. Output buffer is disabled (e.g. selecting the NULL GPIO function)
4. Isolation is clear in GPIO0.ISO, or the previous were true at the point isolation was set
When all of the above conditions are met, the input leakage of the pad may exceed the specification.
This issue may affect a number of common circuits:
• Relying on floating pins to have a low leakage current
• Relying on the internal pull-down resistor
If the internal pull-up is enabled then any floating signal will be pulled high thus removing increased leakage condition as the excess leakage is only sourcing current. This of course can’t prevent the increased leakage if the pad is fed via a strong source e.g. strong potential divider.
Note that this does not affect the pull-down behaviour of the pads immediately following a PoR or RUN reset, because the input enable field is initially clear. The pull-down resistor functions normally in this state.
This issue does not affect the QSPI pads, which use a different pad macro without the faulty circuitry.
The USB PHY’s pins are also unaffected.
This issue does also affect the SWD pads, which use the same fault-tolerant pad macro as the Bank 0 GPIOs. However, both SWD pads are pull-up by default, so there is no ill effect.

Workaround:

If pad pull-down behaviour is required, clear the pad input enable in GPIO0.IE (for GPIOs 0 through 47) to ensure that the pad pull-down resistor pulls the pad signal low. To read the state of a pad pulled-down GPIO from software, enable the input buffer by setting GPIO0.IE immediately before reading, and then redisable immediately afterwards. Note that if the pad is already a logic-0, re-enabling the input does not disturb the pull-down state.
Alternatively an external pull-down of 8.2 kΩ or less can be used.
Note that PIO programs can’t toggle pad controls and therefore external pulls may be required, depending on your application.
As normal, if ADC channels are being used on a pin, clear the relevant GPIO input enable as stated in Section 12.4.3.