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PostPosted: Sun Apr 21, 2024 9:35 pm 
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Location: Ontario, Canada
gregorio wrote:
the behavior of 01011100 (5C) is strange: '5C bb aa' after fetching three bytes accesses FFbb and then spends four cycles accessing FFFF
Yes, that same info also mysteriously appears on a page of my own web site :wink: (and Mr Parker was gracious enough to credit me)

That page is here, and although the $5C opcode holds little promise there's other info pertinent to the topic at hand. But for a more general commentary (though still somewhat 'C02-specific), you may instead -- or in addition -- be interested in what I have to say here (it's a supplement to an article by Bruce Clark here on 6502.org).

The '02 and the 'C02 both have fertile potential for creating new instructions, be they for memory expansion, supercharged I/O, timing synchronization with external events, or whatever else your imagination can dream up. Congratulations to gregorio and others here for going "outside the box" in finding ways that a program can communicate with hardware by producing distinctive behavior which can be detected and used to cue a response. Sometimes this will involve decoding the address bus, but there's also great potential in decoding opcodes as they get fetched (and doing so becomes very straight forward if you have access to the SYNC pin).

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html


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PostPosted: Wed Apr 24, 2024 11:56 am 
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Dr. Jekyll.
I really like your idea. I spent a lot of time adapting it to my project. First of all, I wanted to simplify it to fit into one GAL.
To start with, I chose the codes 02,22,42,62 as "safe", which means that in 6502 no one uses them ;), and in 65c02 they are additional NOPs.
I noticed that to convert code 02 to 8e, 22-ae and 62-ea, you just need to set the d1, d2, d3, d7 bits appropriately and leave the d0, d4, d5 bits unchanged.
If, additionally, the presence of "new" STX LDX codes is signaled at the IO output, I will be able to access the normally hidden IO register. Interestingly, if I extend the IO signal for another PHI1 clock, the register can be 16-bit or 256 8-bit, and if I extend it for the duration of the instruction, I can theoretically get $FFFF of IO registers available in a separate space something like Z80.

Attachment:
File comment: my proposal for a system that converts the JAM codes of the 6502 processor
GAL22V10

schemat3.jpg
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Last edited by gregorio on Wed Apr 24, 2024 1:23 pm, edited 1 time in total.

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PostPosted: Wed Apr 24, 2024 12:06 pm 
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.Now I see that SYNC offers huge possibilities :idea:


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