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Topics | Author | Replies | Views | Last post | |||
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HOWTO: Programming Nexys2 boards from Linux | 7 |
4022 |
Thu Jan 12, 2012 9:31 pm |
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Probably a daft FPGA question... | 4 |
1174 |
Fri Jan 06, 2012 9:02 pm |
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Instruction and Addressing Mode decoders | 0 |
1945 |
Thu Jan 05, 2012 1:51 am |
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Simple Memory Decoder GAL | 58 |
21306 |
Mon Jan 02, 2012 5:13 pm |
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Defining the 65Org32 - addressing modes (and instructions) | 84 |
12610 |
Tue Dec 27, 2011 9:55 pm |
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65Org32 / 65Org16 - interrupts | 0 |
2220 |
Mon Dec 12, 2011 9:41 am |
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Poll: 65Org16 CPU module / general FPGA breakout board idea | 43 |
8197 |
Sat Dec 10, 2011 10:12 am |
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OT: Tiny CPU (for CPLD), subset of 6502, 10 bit addresses | 1 |
2397 |
Mon Dec 05, 2011 12:40 pm |
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Using Xilinx Macros on CPLD | 8 |
1938 |
Tue Nov 29, 2011 9:03 pm |
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Pre-initialized block RAMs yielding zeros upon first read | 6 |
1312 |
Thu Nov 10, 2011 5:27 pm |
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Verilog+VHDL=SystemVerilog | 3 |
1477 |
Thu Nov 10, 2011 5:25 pm |
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UXA PS/2 Interface | 1 |
1018 |
Wed Nov 02, 2011 8:08 am |
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WTH does this mean? | 2 |
1942 |
Wed Nov 02, 2011 8:07 am |
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65Org16.x Dev. Board V1.0 using a Spartan 6 XC6LX9-3TQG144 | 240 |
36145 |
Fri Oct 21, 2011 8:37 pm |
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Free online course: basics of programmable logic | 1 |
2606 |
Wed Oct 05, 2011 8:13 pm |
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Mike Stirling's BBC Micro on an FPGA project | 1 |
2737 |
Mon Sep 26, 2011 5:48 pm |
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More opcodes for the NMOS 6502: Applicable to the 65Org16.x | 13 |
4777 |
Thu Sep 08, 2011 4:48 pm |
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A 6502 SoC Project using a Spartan 3 FPGA | 223 |
52666 |
Mon Aug 15, 2011 11:39 pm |
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Papilio FPGA Shield for Arduino could be GPU for 6502 | 14 |
6495 |
Sat Jul 30, 2011 1:54 am |
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Stepped tutorials on how to do simple FPGA design | 0 |
1935 |
Fri Jun 10, 2011 3:36 am |
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Creating a Video Signal from FPGA Pins | 3 |
2527 |
Fri Jun 03, 2011 2:11 am |
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6502 Verilog Replica | 9 |
7759 |
Tue May 17, 2011 8:23 pm |
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Poll: How to make logic equations for an address decoder | 2 |
4737 |
Sat May 14, 2011 3:13 pm |
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Architecture of FPGAs and CPLDs: A Tutorial | 0 |
1859 |
Sat Apr 23, 2011 3:15 am |
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VDHL | 0 |
2655 |
Tue Feb 22, 2011 1:31 am |
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Amani 64 (CPLD) | 2 |
2008 |
Sat Jan 22, 2011 5:18 pm |
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Getting started with Xilinx CPLD's & FPGA's | 30 |
11641 |
Sun Jan 09, 2011 9:23 pm |
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I'm thinking of getting one of these . . . | 10 |
3089 |
Fri Jan 07, 2011 2:06 am |
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Xilinx manual help | 10 |
3280 |
Tue Jan 04, 2011 3:36 pm |
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The RB65 project | 20 |
6754 |
Fri Dec 24, 2010 9:30 pm |
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Wait-States with a GAL | 50 |
15018 |
Fri Dec 17, 2010 9:46 pm |
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WinCUPL BOOBY-TRAP | 3 |
4625 |
Wed Dec 15, 2010 7:01 am |
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3.3V PLDs and 5V logic | 13 |
6383 |
Wed Dec 08, 2010 6:29 pm |
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65816: question about 8 and 16-bit mode of A, X and Y | 3 |
1934 |
Wed Dec 01, 2010 3:14 pm |
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FLIP-FLOP FLOP | 9 |
5078 |
Sat Nov 06, 2010 8:08 pm |
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VHDL Programming Style? | 5 |
2695 |
Tue Nov 02, 2010 1:51 am |
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65SPI | 0 |
2176 |
Mon Oct 18, 2010 5:24 am |
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