| Author |
Message |
Forum: Programmable Logic Topic: The Mango One - a little like an Apple 1 in verilog |
| BigEd |
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Posted: Fri Mar 20, 2020 11:21 am
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Replies: 0
Views: 2499
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| ... project uses the 8bitworkshop IDE (in-browser verilog simulation) and Arlet's 6502 core, with a subsetted PIA as the interface to keyboard and display - the display being modelled ... |
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Forum: Programmable Logic Topic: A/V SBC with Multiple 65xxx CPUs |
| ElEctric_EyE |
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Posted: Tue Feb 18, 2020 9:33 pm
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Replies: 66
Views: 6952
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| ... I'd used for the later stages of the PVB project. It uses a 65Org16.d core running @74Mhz, 1/2 the video speed. The .d core has a couple more features ... Let me just give credit to those who had helped me get to this stage: Arlet Ottens, BigEd & Michael Morris. I seriously would have not even ... |
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Forum: Emulation and Simulation Topic: Arlet Ottens 6502 - Reset vector not called |
| jstarcher |
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Posted: Fri Jul 12, 2019 5:07 pm
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Replies: 8
Views: 1020
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| ... https://github.com/JeremyJStarcher/kim1-fpga I am trying to wire up Arlet Ottens famous 6502 core within my project, but no matter what combo of settings I use, the RESET vector is not ... |
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Forum: Programmable Logic Topic: Small 6502 systems on Lattice ice40 |
| emeb |
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Posted: Sun Jun 30, 2019 5:00 pm
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Replies: 24
Views: 5890
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| ... at a nice ratio. On the upside I've migrated it from the original Arlet Ottens 6502 core to the hoglet 65C02 core. I really have grown to appreciate those few extra instructions. ... |
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Forum: Programmable Logic Topic: Small 6502 systems on Lattice ice40 |
| hoglet |
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Posted: Sun Mar 10, 2019 9:24 am
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Replies: 24
Views: 5890
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| ... https://forum.mystorm.uk/?order=views Both are currently using Arlet's core, and are working very nicely. Dave |
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Forum: Programmable Logic Topic: Small 6502 systems on Lattice ice40 |
| dmsc |
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Posted: Sun Mar 10, 2019 1:00 am
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Replies: 24
Views: 5890
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| ... is at https://github.com/dmsc/my6502 , it has: - 6502 CPU, using Arlet Ottens core. - A reloadable 16 bit timer module, at address $FE00. - An UART at fixed 115200 baud ... |
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Forum: General Discussions Topic: Semi-OT: "Stories-so-far" - an idea for sharing experiences |
| BigEd |
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Posted: Sun Feb 17, 2019 5:46 pm
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Replies: 5
Views: 809
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| ... built on Chris Baird's and on Ian Piumarta's projects. 65Org16 built on Arlet's core and Nick's easy6502 emulator and came from a broad discussion thread. Electric_EyE took ... |
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Forum: Programming Topic: Code for a Job Handler -- Locator |
| jds |
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Posted: Sun Jan 13, 2019 10:45 pm
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Replies: 35
Views: 3346
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| ... of joint project makes sense too. I've settled on using a FPGA as the core glue of the system, hooked up to a real 65816. I've got that running ... which is not too hard to work with. This is all very similar to Arlet's 6502 Sandbox from which he kindly gave me the schematics and Verilog ... |
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Forum: General Discussions Topic: Introduce yourself |
| KJ6MSG |
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Posted: Sun Sep 16, 2018 3:50 pm
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Replies: 677
Views: 304901
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| ... The current specs are as follows: ⋅ hoglet67's modified Arlet core (65C02) running at 50 MHz ⋅ 32 KB RAM (Xilinx Block RAM) ⋅ 16 KB ROM ... |
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Forum: Programmable Logic Topic: 65Org16 Assembler on custom Xilinx Spartan 6 FPGA Hardware |
| ElEctric_EyE |
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Posted: Sun Aug 26, 2018 4:29 pm
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Replies: 146
Views: 27381
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| ... making the bottom S6 the Master and the top the Slave. BTW, I've seen Arlet's 8-bit core running at 110MHz on a Spartan 6. Those speeds give a new level to software creation. ... |
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Forum: Programmable Logic Topic: 65Org16 Assembler on custom Xilinx Spartan 6 FPGA Hardware |
| ElEctric_EyE |
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Posted: Fri Aug 17, 2018 2:02 am
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Replies: 146
Views: 27381
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| ... Also, for those that don't know, the 65Org16 is a modified version of Arlet Ottens' softcore based on the 6502. That 8-bit core was running over 100+MHz (110 IIRC) on my original ... |
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Forum: Programmable Logic Topic: 65C02 in verilog - extended version of Arlet's core |
| BigEd |
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Posted: Mon Apr 30, 2018 9:02 am
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Replies: 63
Views: 23964
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| Good question - I've asked it on a new thread over here. |
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Forum: Programmable Logic Topic: 65C02 in verilog - extended version of Arlet's core |
| kakemoms |
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Posted: Mon Apr 30, 2018 8:43 am
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Replies: 63
Views: 23964
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| Elsewhere, kakemoms notes that the official supported WDC core runs a lot faster on a particular Lattice FPGA than this extended Arlet core: (WDC 6502 runs at 75MHz on [the MachXO3], Arlets extended 65C02 (by BigEd&Dave) ... |
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Forum: Programmable Logic Topic: 65C02 in verilog - extended version of Arlet's core |
| MichaelM |
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Posted: Sat Apr 28, 2018 1:01 am
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Replies: 63
Views: 23964
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| Thanks for the feedback. I was unaware that my core had been loaded into an FPGA from a vendor other than Xilinx or Altera. When targeted to a Spartan-3A XC3S200-5 FPGA, the predicted maximum operating speed is 28.796 MHz, and after PAR the reported ... |
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Forum: Programmable Logic Topic: 65C02 in verilog - extended version of Arlet's core |
| kakemoms |
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Posted: Fri Apr 27, 2018 5:12 pm
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Replies: 63
Views: 23964
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| The problem may be related to the Lattice Diamond. It tend to underestimate the speed one can get from a core. Your core is somewhat ok (around 14MHz) while the tc_65c02 core by Jens Gutschmidt is reported to only run at 2MHz... Since Lattice also includes the Synplify Pro ... |
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