| Author |
Message |
Forum: General Discussions Topic: A truly self-modifying JSR |
| BigEd |
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Posted: Fri Jun 30, 2023 12:42 pm
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Replies: 18
Views: 12915
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| ... Here's a few results. Beeb with 6502: P Beeb with ICE-T6502 (T65 Core): P Beeb with ICE-T65C02 (AlanD Core): P Matchbox Co Pro 0 (Arlet 65C02 Core): P Beeb FPGA Model B (T65 Core): P Beeb FPGA Master (AlanD Core): P PiTubeDirect ... |
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Forum: Programming Topic: Random-number generation |
| Alex1 |
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Posted: Sat Jun 24, 2023 8:38 am
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Replies: 244
Views: 62396
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| ... inc cnt+3 bne loop inc cnt+4 bne loop inc cnt+5 bne loop rts ./atarisim arlet-new | xxd -r -p | ./rng_test stdin8 RNG_test using PractRand version 0.94 RNG = RNG_stdin8, seed = unknown test set = core, folding = standard (8 bit) rng=RNG_stdin8, seed=unknown length= 2 megabytes ... |
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Forum: Programming Topic: Random-number generation |
| Alex1 |
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Posted: Sat Apr 22, 2023 10:45 pm
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Replies: 244
Views: 62396
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| ... PractRand version 0.94 RNG = RNG_stdin8, seed = unknown test set = core, folding = standard (8 bit) rng=RNG_stdin8, seed=unknown length= 32 ... I remind you that arlet-minimal FAIL on 8kb: state: .byte $00,$00,$00,$00,$01 length= 8 kilobytes ... |
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Forum: Programming Topic: Random-number generation |
| Arlet |
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Posted: Fri Apr 21, 2023 11:31 pm
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Replies: 244
Views: 62396
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| Arlet, you conclude that practrand is not good on 1 KB sets but there is no warning in the ... at 1 kB disappears. The documentation also gives this advice: Most failures on the core tests (other thatn BRank) should have started small and gotten steadily worse as more ... |
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Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| fastgear |
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Posted: Thu Apr 06, 2023 6:03 am
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Replies: 4
Views: 4917
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@Arlet Thanks for the explanation. Everything make sense now  |
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Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| Arlet |
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Posted: Wed Apr 05, 2023 5:30 pm
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Replies: 4
Views: 4917
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| ... because the RDY is deasserted. This is as designed. A normal use of RDY is to add wait states to interface slow memory. This means that the CPU core should wait to grab DI until RDY is asserted again, giving the memory system some extra time to produce the correct data. In this case, you should ... |
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Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| fastgear |
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Posted: Wed Apr 05, 2023 5:17 pm
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Replies: 4
Views: 4917
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| Here are the simulation waveforms. As can be seen when RDY becomes zero, it is as if the a9 (which is an LDA) is discarded. When RDY becomes one again in the other waveform, the system assumes 20 is the opcode (which is an actual fact the operand of the LDA), being a JSR. One can also see resemblanc... |
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Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| Arlet |
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Posted: Tue Apr 04, 2023 6:41 pm
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Replies: 4
Views: 4917
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| Can you attach some screenshots of waveforms? |
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Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| fastgear |
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Posted: Sun Apr 02, 2023 2:20 pm
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Replies: 4
Views: 4917
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| I used the original 6502 core from Arlet Ottens in a number of projects and had great fun with this core. Recently I was working on a project ... |
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Forum: Programmable Logic Topic: WDC/Rockwell 65C02 core with MMU |
| kakemoms |
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Posted: Tue Oct 25, 2022 6:24 pm
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Replies: 26
Views: 13846
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| I started some time ago to modify the 65C02 core by David Banks and Ed Spittles, which is based on Arlet Ottens compact 6502 core. The main focus was a MMU that could help with memory access and protection. ... |
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Forum: Programmable Logic Topic: WDC65C02 instructions |
| kakemoms |
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Posted: Mon Oct 24, 2022 5:18 pm
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Replies: 7
Views: 7937
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| Hi, I have almost finished modifying the 6502/65C02 core by Arlet/David/Ed include the WDC instructions, but I am having some problems understanding how WAI ... |
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Forum: General Discussions Topic: The 65CFF (a chip design no one asked for) |
| 65LUN02 |
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Posted: Wed Jul 27, 2022 11:38 pm
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Replies: 6
Views: 821
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| ... could be saved if the 6502 were actually pared down. Thanks to @Arlet and all my past adventures with his 95% complete Verilog 65C02, this ... a chip design team and fab would have been able to mix a minimal 6502 core with his Woz Machine floppy logic for a 2-3 chip standalone floppy controller. ... |
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Forum: General Discussions Topic: The 65M202 road map that could have been |
| BigEd |
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Posted: Sun Jul 10, 2022 7:55 pm
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Replies: 58
Views: 10909
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| Splendid! I don't think I was aware of this latest adventure of Arlet's - in the thread My new verilog 65C02 core. we're seeing the predecessor project, the one I'm more familiar with. ( verilog-65C02-fsm ... |
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Forum: Newbies Topic: cc65 sprintf with new project |
| mackwinston |
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Posted: Sat Apr 02, 2022 2:53 pm
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Replies: 1
Views: 561
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| ... inside a Lattice (formerly SiliconBlue) ICE40 FPGA. I'm using the 65c02 core from https://github.com/hoglet67/verilog-6502 (which is itself a fork of the 6502 found here https://github.com/Arlet/verilog-6502 ). The whole shebang is running off the primary oscillator which ... |
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Forum: Programmable Logic Topic: CPLD trainer on eBay |
| plasmo |
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Posted: Sun Jan 30, 2022 3:23 am
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Replies: 37
Views: 222924
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| ... possible to install USB Blaster driver in Win10. Bill PS, I downloaded Arlet's Verilog 6502 from GitHub and successfully compiled it with Quartus 9. The resource utilization of 6502 core is lesser than 20%, so Flex10K70 has plenty of resource to hold a 6502 core and ... |
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