| Author |
Message |
Forum: Programmable Logic Topic: Survey of FPGA dev boards |
| enso1 |
|
Posted: Thu Aug 15, 2024 1:04 am
|
|
Replies: 113
Views: 103526
|
| ... see appropriate thread); * The FPGA is not too bad, but a bit slow (Arlet's core maxes out at ~28MHz with 48KB blockram). I miss the nearly-free SRL16 shift registers ... |
|
 |
Forum: Programmable Logic Topic: Tang Nano 9K - a (n almost) perfect 65(x)xx platform |
| enso1 |
|
Posted: Tue Aug 13, 2024 2:11 am
|
|
Replies: 52
Views: 4964
|
| ... crappy, considering a lowly 20-year-old Xilinx XC3S50 can solidly run Arlet's core at 100MHz. I suppose it's possible I am doing something stupid with the DI mux... Note ... |
|
|
Forum: Programmable Logic Topic: Tang Nano 9K - a (n almost) perfect 65(x)xx platform |
| enso1 |
|
Posted: Mon Aug 12, 2024 3:16 pm
|
|
Replies: 52
Views: 4964
|
| ... 65c02 (and Big Ed's?) I've been using from the start for the plain Arlet's 6502 core. Surprisingly, the plain core uses a lot more FPGA resources! These things are so unpredictable ... |
|
|
Forum: Programmable Logic Topic: Tang Nano 9K - a (n almost) perfect 65(x)xx platform |
| enso1 |
|
Posted: Thu Aug 01, 2024 12:28 am
|
|
Replies: 52
Views: 4964
|
| Heh. For the 65c02 core (Arlet-based) to start, the reset has to be asserted for 1 cycle. Makes the reset circuit much simpler. |
|
|
Forum: Programmable Logic Topic: Tang Nano 9K - a (n almost) perfect 65(x)xx platform |
| drogon |
|
Posted: Wed Jul 31, 2024 6:34 am
|
|
Replies: 52
Views: 4964
|
| ... -- in this case I stared and rebuilt over and over a simple harness for Arlet's core until I came across a post here, suggesting holding RESET high for 7-cycles on power-up. ... |
|
|
Forum: Programmable Logic Topic: Tang Nano 9K - a (n almost) perfect 65(x)xx platform |
| enso1 |
|
Posted: Wed Jul 31, 2024 12:08 am
|
|
Replies: 52
Views: 4964
|
| ... -- in this case I stared and rebuilt over and over a simple harness for Arlet's core until I came across a post here, suggesting holding RESET high for 7-cycles on power-up. ... |
|
|
Forum: Programmable Logic Topic: Tang Nano 9K - a (n almost) perfect 65(x)xx platform |
| enso1 |
|
Posted: Tue Jul 30, 2024 6:39 pm
|
|
Replies: 52
Views: 4964
|
| ... $20, is pretty amazing: a reasonably-sized FPGA (a minimal system with Arlet's core is 10% utilization), 48KB of block RAMs, 64Kbit SDRAM, lots of flash, USB for power, configuration ... |
|
|
Forum: General Discussions Topic: A truly self-modifying JSR |
| BigEd |
|
Posted: Fri Jun 30, 2023 12:42 pm
|
|
Replies: 18
Views: 13454
|
| ... Here's a few results. Beeb with 6502: P Beeb with ICE-T6502 (T65 Core): P Beeb with ICE-T65C02 (AlanD Core): P Matchbox Co Pro 0 (Arlet 65C02 Core): P Beeb FPGA Model B (T65 Core): P Beeb FPGA Master (AlanD Core): P PiTubeDirect ... |
|
|
Forum: Programming Topic: Random-number generation |
| Alex1 |
|
Posted: Sat Jun 24, 2023 8:38 am
|
|
Replies: 244
Views: 66838
|
| ... inc cnt+3 bne loop inc cnt+4 bne loop inc cnt+5 bne loop rts ./atarisim arlet-new | xxd -r -p | ./rng_test stdin8 RNG_test using PractRand version 0.94 RNG = RNG_stdin8, seed = unknown test set = core, folding = standard (8 bit) rng=RNG_stdin8, seed=unknown length= 2 megabytes ... |
|
|
Forum: Programming Topic: Random-number generation |
| Alex1 |
|
Posted: Sat Apr 22, 2023 10:45 pm
|
|
Replies: 244
Views: 66838
|
| ... PractRand version 0.94 RNG = RNG_stdin8, seed = unknown test set = core, folding = standard (8 bit) rng=RNG_stdin8, seed=unknown length= 32 ... I remind you that arlet-minimal FAIL on 8kb: state: .byte $00,$00,$00,$00,$01 length= 8 kilobytes ... |
|
|
Forum: Programming Topic: Random-number generation |
| Arlet |
|
Posted: Fri Apr 21, 2023 11:31 pm
|
|
Replies: 244
Views: 66838
|
| Arlet, you conclude that practrand is not good on 1 KB sets but there is no warning in the ... at 1 kB disappears. The documentation also gives this advice: Most failures on the core tests (other thatn BRank) should have started small and gotten steadily worse as more ... |
|
|
Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| fastgear |
|
Posted: Thu Apr 06, 2023 6:03 am
|
|
Replies: 4
Views: 5514
|
@Arlet Thanks for the explanation. Everything make sense now  |
|
|
Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| Arlet |
|
Posted: Wed Apr 05, 2023 5:30 pm
|
|
Replies: 4
Views: 5514
|
| ... because the RDY is deasserted. This is as designed. A normal use of RDY is to add wait states to interface slow memory. This means that the CPU core should wait to grab DI until RDY is asserted again, giving the memory system some extra time to produce the correct data. In this case, you should ... |
|
|
Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| fastgear |
|
Posted: Wed Apr 05, 2023 5:17 pm
|
|
Replies: 4
Views: 5514
|
| Here are the simulation waveforms. As can be seen when RDY becomes zero, it is as if the a9 (which is an LDA) is discarded. When RDY becomes one again in the other waveform, the system assumes 20 is the opcode (which is an actual fact the operand of the LDA), being a JSR. One can also see resemblanc... |
|
|
Forum: Programmable Logic Topic: Arlet Ottens Core and the RDY signal |
| Arlet |
|
Posted: Tue Apr 04, 2023 6:41 pm
|
|
Replies: 4
Views: 5514
|
| Can you attach some screenshots of waveforms? |
|
|
| Sort by: |
Login
Register
FAQ
Search