I'd gladly send them an Atari Antic plus a copy of the datasheet for it if they'd be interested.

I wonder if they'd be willing to convert other IC's as well. I'd love to generate models for other ICs of the 8-bit age.

That's because both of those chips are NMOS. The 65C02 is not the 6502C. :)

Right. Atari's 6502C is just a NMOS 6502 with some of the TTL required for Antic's DMA moved into the chip and predates the 65C02. The 400/800's CPU board contains the equivalent circuit and a stock 6502.

Anyway, the ...

Extending NMI to 8 cycles solved the problem, so another small 6502 bug for the list (although I don't yet know how many cycles it must actually be, I've proven it's 8 or less).
I wonder if that's basically the same as the IRQ-coinciding-with-BRK-instruction bug which was also fixed in the 65c02 ...

Another AtariAge topic I participated in...

http://www.atariage.com/forums/topic/148595-how-can-pokey-irq-timers-mess-up-nmi-timing/

Although the original 6502 documentation states that an NMI pulse only needs to be 2-cycles to be acknowledged, this isn't true if an IRQ happens at the same time ...

Never mind. It doesn't work that way.

Can someone verify something else? According to the datasheet I'm looking at, you must read port A to clear the interrupt. However, writing to it seems to work too.

Question...

If I'm using CA1 or CB1 as an input, and I flip the polarity bit (bit 1 of CRA, CRB) without any change on the actual CA1 or CB1 line, will anything happen?

What I'm kind of wondering is if the polarity bit inverts the incoming signal generating false interrupts as the bit is changed ...