For eliminating the dead bus cycles, I would have nothing against running the processor at 4 or 8 times the bus speed so the processor can do more steps per bus cycle. In fact, this would allow running bus faster with the same memory speeds, and better set-up and hold times could be guaranteed ...

It does not matter if DEC doesn't drop MLB during the fetch, because it already owns the bus during the fetch. When the CPU relinguishes the bus for its internal operations, then it drops MLB so that no other processor uses the otherwise idle cycle, thus preventing potential changes to the read ...

Does a DEC absolute $00xx do the same ?

--Jorge.

The (old) datasheet specified that MLB was active (low) for the last 3 cycles of a RMW instruction. I have found experimentally that this is not the case, at least with the DEC zp opcode. MLB goes low on the dead cycle after the first data (read) cycle, stays low for the next cycle (write data ...

Me too..

--Jorge.

The dead-bus-cycle decoder could simply rule out access during the unpredictable cycles in instructions that have variable lengths depending on decimal flag and whether or not a page boundary is being crossed in indexing, and you'd still be left with a substancial chunck of DMA bandwidth. If you ...

I've had my PC chugg through the code that's running my bench computer. Using the dead cycles, I can rely on a bus bandwidth of about 60-70 kbytes per second per megahertz, with a peak performance of three times that for certain blocks of code. However, there is also a point in the code where there ...

Hallo Jorge,

That's what I think that's the whole point about this idea...

First: I forgot to say that the idea on itself is very good!

And even after a second and third thought I have my doubts but please don't let that spoil the fun for you. I really hope you get it working.

Hi ruud,

For ...

Definately an intresting idea. But whatever is using the transparant DMA chanel must be something that can afford to wait a bit for its data. Otherwise, the processor is going to execute a section of code that has few dead cycles at the wrong time and really screw things up.

That is the big ...

Hello All,

Interesting idea indeed.
Assuming a systen already set-up for DMA access and already using
interleaved memory access (video controller?) this has potential to
eke-out a bit more bandwidth for (almost) free. Check me on this:
DMA access throughput (during dead cycles) will be mostly ...

Hallo Jorge,


To be honest, IMHO to much trouble to get those 199 KB/sec.

(..)

I rather prefer the two CPU solution as used in various Commodore drives: two 6502's running on the same data bus and sharing the available memory. And why should the second CPU be a 6502? IMHO you can use every ...

Without spending much time on it, it looks like it should work as long as certain limitations are kept in mind. For example, certain instructions are one clock longer in decimal mode than in binary. The logic might also have to know if interrupts are enabled and watch the IRQ and NMI lines (+ ABORT ...

Hi Jorge,

links to
http://homepage.mac.com/jorgechamorro/a2things/a2DMAMagic/index.html

I don't think anyone has ever done this. Every system I know relied on guaranteed throughput and is using the RDY line or Phi2 magic to actually stop the CPU.

But nice idea, though. I am currently in the ...

http://homepage.mac.com/jorgechamorro/a ... index.html

Has this ever been done ?
What do you think about it ?

--Jorge.