The best logic family for general use these days is probably the 74HC... series of devices. These are CMOS versions of the earlier 74... and 74LS... devices.

If you want to run at high clock speeds, the 74AC... devices are what you need.

If you want to use SYNC to determine whether to select ROM or I/O, you don't need to decode the instruction and work out how long the operand is. Simply assume that all instructions are three fetch cycles long. Any shorter instructions are either 1-byte long, in which case they only perform internal ...

When I was at university, some of my clever fellows realised that it was possible to add write-only I/O devices to a system without losing any of the memory map. Simply enable the ROM for read accesses only and then re-use the same addresses for your write registers. Since the ROM was a 16k device ...

It's looking good. One question, will you be adding PAL capabilities to the CPLD for us europeans? I know the AD724 can do either with just a change of the oscilator frequency and a jumper on the mode select pin.

I am feeding a 14.318MHz TTL Osc into my 95108 CPLD and dividing it down to 7.159MHz to feed the PHI2 on 65816.

Using a 50Mhz Scope, the clock waveform looks terrible on both the TTL oscillator and the PHI2 output. I recall "Kc5tja" having issues with slow rise/fall times on the 65816 clock. I ...

Will your design do PAL or only NTSC? If it does PAL, I will be very interested in it.

I believe test mode makes the processor execute reads from successive addresses, effectively making the address bus function as a counter. The only way to get the processor out of this mode is a reset - it won't respond to interrupts. The instruction that causes this behaviour is HCF (for Halt and ...

Ohhh yes, very nice. I wish I had one of those 25 years ago when I was just getting into computers, I could have had so much fun. If it comes to that, I wish I had the money to afford it and somewhere to put it now!

Plenty of classics from the 19670's

Yeah; that was a good century. But, you gotta admit, the 19750 to 20210s were much better -- that's when we invaded the Alpha Centauri to put those Centaurians back into the information age. ;) Goes to show them that you can't mess around with a civilization ...

The HC574 is easier to fit into a PCB layout than the HC374, its basically the same chip in another package. See my earlier post.

I've looked over the schematic for the 8-relay card and I've found a fairly major problem with it. :(

There is no latch on the outputs that drive the ULN2803 device. This means that the relays will only be driven for the brief period when the processor actually writes to the output - in practice ...

I've had a look at the schematics for Daryl's SBC. He takes the 8 I/O select lines (7F0x - 7F7x) and the I/O page select line (7Fxx) out to the expansion connector.

All you need to do is gate these lines on your expansion card to create an enable signal for the 74HC245.

A single-chip ...

I've just checked out youe schematic and I'm afraid I've found a couple of problems :(

1) You've got the 74HC245 on the data bus the wrong way round. The B port should connect to the CPU and the A port to the expansion bus. Or you could keep it as it is and invert the R/W\ line that feeds its ...

You could always use a 74LS148 priority encoder.

I've looked into this chip - I mention it in an earlier post - it certainally seems to do what is required and is currently my favourite option.

Looking at the datasheet, you would only need to OR (negative logic AND) the GS and EO outputs ...

Thanks for the contact - I've just placed an order with them.

Soon I will have a 65C816 and can find out what this 16 bit stuff all you guys go on about is really like