This doesn't look like sensible Verilog to me.

Specifically, you are assigning to signalChangePending in two seperate blocks, which is not legal.
Aha! Thanks, that's what I was missing. I didn't realize there was that restriction. Changed the example to this and it builds as expected:
module ...

Hey hoglet, I've hit some synthesis errors I don't understand with the yosys toolchain, wondering if you could take a look? Here's a stripped down example:
module Bug
(
output reg signal,
input wire CLK
);

reg currentState;
reg signalChangePending;

always @(posedge CLK) begin
if ...

You're right, my bad. I've only used SystemVerilog prior to now, I probably have some more incorrect ideas about the differences rattling around.

Will do. I forgot to mention in the commit, I didn't preserve the workaround for reversing the port bit order, so the Windows scripts assume Yosys version 0.30+21 or greater.

Have you done any tests with the Synlig plugin for Yosys out of curiosity?
https://github.com/chipsalliance/synlig ...

Bump to say that I've just submitted a pull request for https://github.com/hoglet67/atf15xx_yosys which adds Windows batch scripts to make this toolchain easily accessible for Windows users. I plan to use this over the next few weeks to test out programming ATF1508 devices under Verilog using this ...

I'm also starting out with an ATF1508AS, so I'll probably have something to contribute here eventually. I'm aiming to program in SystemVerilog exclusively without paying for the commercial packages, but I'll have to see how I go with that over the next few days. Also, if you haven't seen it, I ...

Board arrived and assembled. Chip detected and passed blank check in ATMISP, thanks!

Thanks for this, I'm starting to build a few devices using the ATF1508, and this breakout board is brilliant, much better than what I was just about to throw together. Doing a fab run now, much appreciated!