SN74LVC1G17 Schmitt buffer in par w resistor for self-latch.
Not at the floating open output, but at the confused input.
Hold last strongly established state with weak bleed-back.
Never tried, could be talking nonsense...

Forgot AUC2g06 dual OD inverter. +AUC06 hex leaves no unused spare.

Not so worried for nonsense flag cases, except V for BIT should echo F6.
After studying 6502 instruction set, every flag has cases to deny change.
Thought about multiplexing original values back, but simpler to not clock
unwanted ...

No clue if this NotZero could actually work.
Throwing stuff at ceiling to see what sticks.
WidlarZero.png
Obviously NOR style Zero using inverters would be preferable.
Trouble is finding a good enough PNP.

I've tried KSP10 before. Impressive NPN.
Replacement for gold doped MSP10 I think.
Tried as ...

basic 8 function ALU (Add, Subtract, Shift Left, Shift Right, AND, OR, XOR, Negate)
Shift Left, Shift Right, and Negate only require one operand + Carry. Frees B to select of 256 Subfunctions.
Moving them all to one function frees a pair of dual operand tables for 6502 Decimal mode Add and ...

Lookahead tree for logic Zero is Karnaugh then NOR8.
Can't make any simpler than straightforward solving.
Greatest problem, no part offers wide enough NOR.
Open drain 74AUC2G06 loaded with current mirror?

NVCZ.png
Let the complaints begin...

Looking back upon this, I see the Overflow XOR gate could have been 5V LVC.
Inputs are 6nS earlier than full results, so plenty of time for the slower gate.
Also plenty of time to buffer the Carry output. Prolly should have done that.

The Zero chain can't ...

"intermediate" "tripling them will add too much capacitance".

Triples both capacitance and conductance. RC remains exactly the same.
No unloaded timing difference three strings separate or bonded together.
Bond is not helping, but also not making worse.

Except the fanload of XOR gates now appears ...

Not the only one that can copy/paste...
LVC.png
AUC.png
Neither LVC or AUC look much like your theoretical figure 2-4.
Not sure what logic family inspired that graph with a mid dip.
Can't be HC we were looking at, resistance too low to be HC.
TMUX, CB3Q? Something boasting more VGates than 4.5V ...

"As you can see, the Rdson is growing exponentially with the supply voltage"
No. Supply voltage was a constant 5V for that graph. Sais so at the bottom.
You are reading the graph entirely inside out.

Resistance rises with the voltage in the channel, not on the gate.
Resistance I've measured. <3 ...

Let me be more specific: I don't believe AUC2G53 transmission gates provide best propagation.
Totally on-board with AUC as combinatorial logic, but the transmission gates don't benefit from
triple output totem with diodes and feedbacks. Gate drives maybe, not what is passed through.
Not enough Volts ...

How to BCD??? Multi-step might be simplest.
Add +33BCD to each operand to make Excess33.
Shouldn't be enough to trip C4 or C8 assuming
only valid BCD starting numbers are ever input.

XORvert Excess33BCD_B for option to fake Addition.
Result = Subtract(Excess33BCD_A,Excess33BCD_B)
Subtract should ...

Have 35nS MRAM for that. 21 Address in, 8+8 data in/out.
Save cheating for complex operations I can't MUX faster.
Cosines, Division, Remainder, Root. Fixed points HL.XYZ

Need primitive functions before tables can be indexed.
Self-index is a cycle wasting juggle of external latches.
Not saving time ...

No, I broke up the Elmo problem to not much worse than a single 4way chain.
If I had abused 8way (and I did not), that would be a huge parallel capacitance.
No need to convince me that stupid pet trick would Elmo face first and hard.

The rotation 4way adds capacitance to each tap, yes, but worth it ...

Oh, so V=XOR3(C8,F7,F6). I guess that works.
But can't start till we have Full F7,F6 results.
Was thinking V=XOR2(C7,C8)
Same rule for Borrow /Borrow.
Can begin figuring V 6nS earlier...

Unless V is inverted for a 6502 borrow?
I assume V overflow true regardless why.
Correct or incorrect, need to ...

For subtraction (A - B), are you contemplating inverting all the 'B' inputs and setting the carry, and leaving the adder as it is? It sounds like it from your description.

I think this makes subtraction slightly slower than addition, but saves a lot of parts - XOR gates being two or three gate ...