Search found 3 matches
- Thu May 18, 2023 2:50 am
- Forum: Programmable Logic
- Topic: Verilog to WinCUPL generator\workflow
- Replies: 29
- Views: 31849
Re: Verilog to WinCUPL generator\workflow
Coincidenally, I also had a go at this a few months ago:
https://github.com/hoglet67/atf15xx_yosys
Hi Dave,
Thanks for pointing this out to me. I like your process, its more elegant I think than code generation. Its ironic that you are using WINE, because I couldn't get WinCupl to work ...
- Thu May 18, 2023 2:08 am
- Forum: Programmable Logic
- Topic: Verilog to WinCUPL generator\workflow
- Replies: 29
- Views: 31849
Re: Verilog to WinCUPL generator\workflow
[...] I've come up with a handy way to generate WinCUPL from Verilog using Yosys and a simple utility I wrote called JsonToCupl. Coincidenally, I also had a go at this a few months ago Mike, Dave,
What hardware and software are you using to program the ATF15XX devices? I'm using minipro with a ...
What hardware and software are you using to program the ATF15XX devices? I'm using minipro with a ...
- Sun May 14, 2023 4:43 am
- Forum: Programmable Logic
- Topic: Verilog to WinCUPL generator\workflow
- Replies: 29
- Views: 31849
Verilog to WinCUPL generator\workflow
Hello,
To anyone who may be interested, I've come up with a handy way to generate WinCUPL from Verilog using Yosys and a simple utility I wrote called JsonToCupl. You can find this utility on GitHub https://github.com/michaelhunsberger/JsonToCupl. Yosys is a free and open source tool for digital ...
To anyone who may be interested, I've come up with a handy way to generate WinCUPL from Verilog using Yosys and a simple utility I wrote called JsonToCupl. You can find this utility on GitHub https://github.com/michaelhunsberger/JsonToCupl. Yosys is a free and open source tool for digital ...