While I've got everyone's attention, here's another question along the same vein.

I've read that the 6502 uses a sort of instruction pipelining, such that if a write isn't done on the last cycle of an instruction it pre-fetches the next opcode. My question is about the BRK, JSR, and JMP ...

Thanks, that cleared up some things, especially with regard to the indexed addressing mode. My books finally came in so I think I'm set to start some serious work on my simulator.

On the suggestion to keep all your I/O ports on one page, that seems like the best way to avoid the indexed addressing ...

Hi, I've run up against another problem on which I'm having trouble finding information. I can't find out in detail how the NMOS works with respect to the "garbage" reads and writes it performs during certain instructions. The CMOS chips are predictable from the documentation I have, but I need to ...