Dang: 10b)
In the schematics, it's low_active INT_ACT#, and that's correct.
In the chip pictures, that signal is labeled INT_ACT, high_active, and that's not correct. Fixed this. :roll:

Just for you, a quick drawing made from your 6526 ICR guesswork:
Great! This covers the only part of the 6526 ...

Using the MOS 8521 vectorization as reference, and with a bit of guesswork, I think I managed to make sense of the MOS 6526 ICR block.

In short, 10a) (ICR bits 0 - 4) is functionally equivalent - it just omits two inverters in series in the W_IFR path.

On the other hand 10b) (ICR bit 7 and IRQ) is ...

Hi Dieter,

Wow, that was fast!


10a) / 10b) Driving of ICR register outputs to 0 is delayed by a cycle. I'm
guessing this is caused by capacitance delay in rather long polysilicon gate
strips when these are driven by the positive output of weak inverters, but
this is above my pay grade :-)
Hmm ...

Hi Frank and Dieter!

I have just finished a MOS 8521 FPGA implementation based on your excellent work - kudos to you!
See https://github.com/daglem/reDIP-CIA

Here are a few comments / corrections which you may want to incorporate.

8e) / 9e) TA_Q and TB_Q should be inverted (same polarity as TA ...