Ha!! I freakin did it!!!

Okay so here is the basics, the 'clk' is a 100mhz clock for the ram and signal gen and is skewed back 30 degrees. hdmiClk @ 250mhz and vClk is at 25mhz are synced. The HDMI encoder sets the rgb/hsync/vsync/vAct off of the vClk which, again, is 30 degrees ahead of the ram ...

I should resurrect this project, as it's quite fun!


I think there is a need for a good open sourced FPGA Video controller, TBH this is the main reason the Commander X16 is interesting to me, I wish they'd open source the Vera. As far as I can tell they are using an ICE40 which can be had on ...

All of my clocks come out of a single MMCM clock generator and I have no skewing.

Thanks for both of your input I will dig into that deeper, and I'm happy to hear of someone else who had done the same that I was attempting, I'm hopeful that will give me some real insight.

Hey Guys,

Been working on an FPGA Video controller for my FPGA project and one of my big struggles has been the Video Ram. Running real time assignments giving the CPU priority to the ram works great, apart from the video artifacts, especially during large writes.

The ram is 10ns, the Video ...

Just to post a follow up on this subject.

This is resolved and here is sort of the final state

On the rising edge of the video clock I latch in the horizontal and vertical counters which are piped over to the ram

on the negedge of the video clock the video positions are latched into a buffer ...

As of the last update I thought the open drain output wasn't working on the FPGA, but it turns out it was, the pullup on the 5v side just wasn't nearly strong enough. I've since replace the 10k with a 220 on the 5v side and it is pulling up to just over 4 volts and working. Lowering the resistance ...

The 5v side connects to a 6522, 6502, and an ATF1508, the 3.3v side only connects to a 3.3v pin on a Mercury II fpga.

The idea behind the circuit was to allow for a clock on the 5v side to be present and down translate to 3.3v to a clock pin on the FPGA, or to allow the fpga to drive the clock ...

Hi guys,

Running into a bit of an issue with one of my designs. I'm using an LSF0102 to translate between 3.3v and 5v. It's an open collector translator and is supposed to do bidirectional translation, but I can't get it to uptranslate to 5v, it will only output ~3v on the 5v side (b).

Currently ...

Good morning all,

Currently working with an ATF1508AS-7AX100 coding in Verilog on Quartus II 13.0 configured for a Max7000s EPM7128STC100-7.

The problem I'm running into is with my soft power/reset circuit. The reset works perfectly both with button interaction and power on reset. The problem is ...

grounds are on the right. The expansion card sits on top of all 3 headers. Below is a 3d rendering of the serial io card I have on it.

Hi guys,

Upgraded my initial 6502 board design and I have left over 4 untouched PCB's compatible with the Commander X16 addressing using some Atmel PAL's for address decoding and soft power circuit using an ATTINY. The board works great, but does require a single bodge as I failed to connect the ...

Hi All,

I have a Mercury II Artix 7 based FPGA interfaced to my 6502 project to drive my video through HDMI, It's a good solution that seems to be working pretty well so far and I'd like to leverage the included ADC and DAC for line in audio to load old programs, as well as use the DAC to build a ...

Hi guys,

Not sure if this is okay or not, but I'm having some trouble locating a couple parts I need and was wondering if maybe one of you all happen to have some spares, or know of a resource where I might find them..

1. DM3AT-SF-PEJM5 - Micro SD card socket
2. RN4871 - Bluetooth module

I'd ...

It is 50mhz, sorry i was thinking of another resolution i was trying that ran on 40. The picture was taken at 50mhz with the attched code in the forst post.

Did you happen to see anything wrong?

What kind of connector are you using? Does it connect directly to the FPGA through circuit traces? Using a ribbon cable for instance will pick up a lot of noise.
What does the timing circuit look like? Are the sync signals registered outputs? Are the ram address signals registered? Is the address ...