Ok, guys. Flags are hard. They are the worst part of the design. I made them addressable and i regret doing it.
I regret it so much that now i will remove addressable flags and put 2 special instructions to load and store flags. This will simplify the design a lot.

I had this weird idea about implementing interrupts and jsr/bsr with the same circuitry.
After all they look the same, push pc first and then jump to address (address = pc + offset if bsr).
I hope it doesn't turn out too difficult to manage.

Good news.
I fixed another ton of bugs. Now this program Run correctly in 812 cycles.

Update.
it reached alpha stage. I have to fix the decoder, the internal core seems to work. Fetch seems to work too.
Simulated with iverilog. Synthesis seems to be fine with yosys.
I discarded short instructions, they are infrequent and not worth the hassle. Poor decisions were fixed (e.g. reset to ...

As Druzyek pointed out in another post, CC65 produces more efficient code.
I compared some code that I have been working on and found that
WDC comes in at 1922 bytes (CODE)
CC65 comes in at 1860 bytes (CODE)
In fact CC65 does even better as I had to remove the UTOA function from WDC as it was not ...

You are wise to avoid 64 bit extension until the instruction pipeline is working. FPGA addition is O(n log n) and therefore basic functionality, such as ALU, may bloat more than expected - with consequent performance loss. (Even when treating a microcontroller as a convenient microcode ...

Hi Sheep64!
Well, point per point:


I am alarmed when people work at a blistering pace. I think that I'm either making hard for myself, the other person has missed a fundamental problem or they have vastly more talent than me. Given your apparent competence with instruction pipelines and micro ...

Up.

Still working in the decode stage. I hope to avoid the generation of many muxes.

Fetching unaligned opcodes is bad. It require 3 port memory and double the amount of logic (2 adders, 1 for PC, 1 for Next).
It could have been worst, i had only 16b/32b ops. Original 6502 with 8b/16b/24b would have been a mess.

On the good news i mostly need to port the decoder to verilog to ...

There are some bug in LogicCircuit regardings bits. With the complexity of the back end, some bits become missing, then they reappear at the next cycle. I found a few bugs in the decoding and a miscalculation of timing, i accidentally overwrite a value in the constant register one cycle before it is ...

It's me again.

The following program now correctly gets decoded by the Front End:

_reset: LDA:Y #100
LDA:A #$C000
STA:A $A0
LDA:A #$B000
STA:A $A2
_loop: SUB:Y #1 ?
LDA:A byte ($A0),Y
STA:A byte ($A2),Y
BNE _loop
LDA:A #0
STA:A byte $FFFF ; stop the clock


Without manually setting the ...

mysterymath, are you using cc65's routines for signed comparisons, 32 bit arithmetic, etc?
Or are you developing them independently?

EDIT: spelling

New Update:
I must have been drunk when i wrote "Fetch now works".

I found 4 bugs in 5 minutes this evening:
1) My CPU ops are 16 or 32 bit. I did not even put the required signal (pc_inc_2) in the fetch module. Now resolved.
2) I forgot about the behaviour of the hold signal. Now fixed.
3) Fetch ...

Yes, sorry.

Is it open source or proprietary?