It's great to see the progress on this! What is the deadline?
For the shuttle I ended up on, may 11th: https://app.tinytapeout.com/shuttles/ttsky26a
Here's a link to me! https://app.tinytapeout.com/projects/3829


I stuck more rigidly to RISCV's principles, for better or worse - this had a fair ...

Note that NMI here is special, not like a 6502. In particular, you can't necessarily return from an NMI. It's meant for watchdog resets, power brownouts, and the like.

Edit: I see this as a valid and interesting design choice.

Yeah, this was something that I ran into when examining how RISC-V ...

It might be worth looking at the 6530 RRIOT die, compared to the 6502 die, to see what the size of that 16x8 register file might be. Of course, a 2R1W is going to be a bit bigger than a simple SRAM.
http://retro.hansotten.nl/6502-sbc/6530-6532/tim-6530-004/6530-004-dissected/

The z80 has, of ...

(To some extent the 6502 is jointly transistor-limited and also interconnect-limited - one layer of metal, needs to carry power and clocks and some proportion of signals. But still, an interesting project and an interesting comparison!)


You're the second person to point this out; it's a valid ...

Well, after much vibe codery, Claude and I have managed to get a design ready for Tiny Tapeout!
https://github.com/mysterymath/riscyv02

You can see a cool 3d view of the die here: https://mysterymath.github.io/riscyv02

Highlights:

8x 16-bit general-purpose registers (vs 3x 8-bit on 6502)
2 ...

A very interesting project! Any updates on its progress?

I'm still at it! I hadn't done much work on it in a while; dealing with verilog is *very* tedious, and I couldn't get the tests working. Thankfully, Claude is rather good at verilog, which has allowed me to try a lot of ideas very quickly ...

I also apparently was out of date with my notes compared to my actual implementation doc. It looks like I was able to fit these additional instructions:
- J: Jump (JAL, but leave link register alone)
- JR: Jump register (JALR, but leave link register alone, and with a wider offset)

As an aside, I feel like a pipelined 4 cycle 32-bit RISC-V implementation with roughly the 6502 8-bit bus would be a lot of fun to build using this approach. Maybe some other time. (Or some other person ).

If the RISCY-V02 used an approach that broke each computation into multiple 8-bit chunks then, as well as 16-bit, perhaps it could also (with a slight penalty) execute some 24- or 32-bit operations!

Aha, you discovered my clever trick, but in reverse. The ALU is already 8 bit; I'm taking ...

Is "register x3" simply one of the general registers, but one with special meaning in regard to this instruction group? Also, why the choice to restrict the load/stores to using only a "base" register ("any of the first 4 registers")? Is this to limit that particular bit-field to only two bits so ...

Yep, this was cribbed from RISC-V. JAL gives a near call, AUIPC/LUI hi + JALR lo gives a far call, and JALR 0 on the "link register" gives a return.

Looks like you've invented the PDP11 :)

Kinda, but not really? If you squint at it, the ISA characteristics are similar, but a RISC is a pretty big departure from an orthogonal instruction set. It's decidedly non-orthogonal: there's only one addressing mode, and only dedicated load and store ...

One of the difficult things, in any retro-engineering effort, is making the decision of how historically accurate you would like to be in your work. Do you want physical hardware, or is emulation enough? Is it legal to use modern tools and technologies, or must all your tools be period-correct ...

Because I figure this will immediately come up:

How do I do this?

LDA #42, STA 1234?

That's 5 bytes, 6 cycles.

In RISCY-V02:

LI r1, 42
LUI r2, hi(1234)
SB r1, r2 + lo(1234)

That's 6 bytes, 7 cycles.

But, afterwards, there is a little 128-byte "zero page" centered on r2:

LI r3, 43
SB r3 ...

I was thinking of restarting a stalled project, and I wanted to consult the 6502 expert oracle about it.

Here was my question: was the 6502 a "historically optimal" design? A lot of people think that it's impossible to have done better at the same size, regardless of what we've learned about how to ...