Hi again Marco,
forgive me if I edited my previous post while you had already answered, we were writing almost simultaneously and I hadn't refreshed the page in the meantime for me to read your last reply.

Regarding your last note about a preference on Verilog/VHDL, I didn't mean to revive the HDL ...

Hi Marco,
as I wrote before, I had already analyzed your code in comparison to the behavior of a real 8722; what I didn't know was the purpose of your implementation and the kind of feedback you could have liked to receive (I had also checked your website, in order to understand your main interests ...

Hi Marco, thank you for your reply.

I understand what you mean, still I had read your request for feedback as an intermediate stage to go for a complete implementation (a "clone" as you named it) of a real MMU8722, a chip that you showed to know pretty well and that - let me say - is an objective ...

Still one note regarding the DBE signal...

You have implemented this input in order to (externally) manage contention on the cpu data bus when registers are read, still in a real 8722MMU there is not such a port and there isn't any external "chip select" detection logic for the MMU in a C128. So ...

Hi Marco,
I've just checked your "clone_8722" verilog code against the expected functions from a real 8722 mmu and, as you were looking for some good feedback, I'm going to provide you some.

First of all, there are some inconsistencies in referring to the MMU registers and so to naming the related ...