I've been studying the schematics of the old machines to learn about how dynamic memory refresh is implemented.

The PET 2001 schematics are available onine, and I'm looking at the main board (part 320349). (The schematic PDF is https://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/2001N ...

These configurations work! I've got a 2732 in U21, and another in U22. These jumpers map C000 and C800 to U21, and D000 and D800 to U22.

It'll be a bit before I can actually test BASIC because I need some female DB-9 connectors, but poking around with the mem command looks like everything is ...

I have to disagree.

When it comes to benchmarking, it is vital that someone else can reproduce your result.
Seconded. While the benechmarks and results presented here are certainly fun, I wonder what's really being measured. Machine-to-machine speed is lost, since the performance of a BASIC ...

Yep, that's what I used to try to cook up this jumper configuration.

I've finally got my board working again, so I'm going to try to rewire the jumpers this week.

I've been scouring the manuals to figure out how set the jumpers to get a pair of 2732 chips with BASIC into my SYM-1.

Does anyone have a source for a SYM-1 schematic? There's one in the "theory of operations" manual PDF file, but it's split over several pages and missing information ... and, of ...

A typo for the PBR. So very sorry to not perfectly enter my thoughts. We can look up the PLB instruction, though, and see that it's target is indeed the PBR. So at least I got it half right!

Uh...there is no PLK instruction. In fact there is no direct programmatic means by which PB can be modified.

I think that's a typo for PLB, which is "pull data bank register from stack".

Thus, my suggestion of getting a value into A, pushing it, then popping it out into the PDR with the PLB ...

The easiest way to set the PBR, incidentally, is to execute a JML instruction (JMP with a 24-bit address). That does set the PBR, but I don't think it works well in the context of the mapping switcher hardware that you're designing.

It'll take about half a million cycles, which is an eighth of a ...

My recommended sequence would be to copy the contents of the ROM into the area of RAM that will appear in high bank 0 before switching to native mode. What's the rationale for your recommendation? Takes a little while to copy 32K, avoided by initializing the PBR before the switch (if that works ...

At some point the programmer may choose to alter PRB and/or DBR, but it'll be at his/her convenience

I'm looking at the decoder and clock manager at the bottom left of Chromatix's schematic.

It's not too clear to me what the 573 latch is doing becaues the latch inputs and outputs aren't labelled ...

It's probably worth a few extra eyeballs making sure there are no glitches here and that the timing I think will result is correct.
Have you built these? I'm wondering how the transition from emulation mode to 16-bit mode works. If code is executing at a ROM memory address when the transition ...

Thanks for all the tips, everyone; and thanks for the welcome and encouragement too :)

There's more reading to do, but I think that I can lay-out memory mostly at will since the long-addressing instructions do exist. Once the zero-page, stack, and vector tables are in place, I'll try to keep ...

Thanks! I guess I'll go with the TL866II, then ... I can't justify double the price for the newer model.

I've been looking at device programmers. For sure, I want to program 27xx series EPROMs. Plus, some of the EEPROMs that are pin-compatible to that series, like the WinbondW27Cxx chips. They're faster, and I can skip the UV erase cycle. Probably end up using PIC chips, GALs, and some CPLD devices ...

As for getting started, I'd be more inclined to leave the SYM-1 alone (I've got one as well)... as you can build a very small SBC which is much faster, has more RAM and ROM, and adequate I/O to get started and you don't need an erector set of parts and boards to connect to the SYM-1... but of ...