Thank you for the comment and images.

Yes, two CPUs run with no wait except the arbitration case. Thanks to the BE signal, no bus buffer is needed. The signals MLB, RDY, and BE make SMP so simple. the design of 6502 signals is great, I think.

memory space (can be configured easily by programming ...

Hi,

I made a dual 6502 SMP system. Bus arbitration is performed by MLB, RDY, and BE. Read-modify-write instructions such as INC are treated as atomic operations. You can implement mutexes by using LSR, for example.

https://github.com/hatsugai/Dual6502

hatsugai

I wrote a code generator of CCLV for 6502 (W65C02S) and measured the execution time of fib and tarai.

I wrote a code generator of CCLV for MC6800 and measured the execution time of fib and tarai.

Thank you for the information.

I was surprised to see the deep discussions.

I seem the tarai function is suitable for this kind of benchmarks, especially for measuring the performance of procedure/function calls.

Dr. Ikuo Takeuchi, the inventor of the tarai function, is famous as a Lisp hacker ...

The benchmark result of MC6809 is corrected. (I miscopied.)

tarai: 54.421 sec -> 51.421 sec

hatsugai

I fixed a number of mistakes on the schematic.

hatsugai

Thank you for your kind comments.

hatsugai

Hi,

I made a 6502-based computer for high-level programming languages.
I also wrote a tiny compiler for the computer.

https://github.com/hatsugai/Fenestra6502

hatsugai