Is there any point to running it at 14MHz in a complex design?

It seems any data to be 'read' by the processor must be presented in 35ns, including all your decoding. A CPLD/FPGA can easily decode fast enough, but DRAM tops out at 60ns. So, every time you access DRAM, you have to have logic that ...

Ahh, yes, I forgot about that!

I forgot to look for all the little people running in terror from it.

Tho....I WAS poking it into the I/O Tower!

And I slowly learn more and more.
I found the logic probe my dad gave me a couple of years back. Darn thing works, I think.

It shows a square wave being input into XTALI, and something stuck at HIGH on RxC after I store a 0x18 into 0xDE03 (Control Register)

Prior to this, RxC has nothing on it at ...

Actually, seems as if i can transmit 1 byte no matter what I do now.
Caps or no.

Hmm, I put a 33pf cap on (all I had), and now I can poke ONE byte (dunno if it goes out) before it gives up and stops emptying the transmit buffer.

Hmmm, okay. I'm using a oscillator rather than just a crystal, so I'd assumed the caps were not needed. However, I'll try that tonight!

Not, of course, that any of this is in the schematics floating around the net for building this. No caps or anything.

Yeah, I looked through my PRG more carefully. Seems, and I shouldn't have been surprised, that even when the 128 is in 1MHz mode, it still generates 2MHz timings around the rising and falling S02 clock. Just less frequently.

The address hold time is a max of 40ns on the 128, with the 1MHz part ...

ARGH!

Okay, the thing about the softie with the soldering iron is all true. Ow. :)

If I understand what you're saying a 1Mhz 6522 (in your example), hooked directly to a 1Mhz 6502 would work fine. But, since the memory of the C64 and C128 is layered and banked, there is a significant delay between ...

Okay, this ISN'T an exact match of forum, but it DOES involve the task of interfacing something to a 6502 based system.

Basically, I'm trying to hook a 6551 to my 128's expansion port. Got a little breadboard going, and I have the following results.

With a CMD G65SC51P-1, the address lines behave ...

Umm, dunno! But....are you really hooking up SDRAM to a 6502 based system? Have you got it running THAT fast?

*pictures LN2 cooled 6502 overclocked to 3GHz*

Hmm, after writing that, I see your point about latching in each new interrupt. It's almost a simpler design to simply have 8 flip-flops rather than trying to 'encode' it into 3 bits. Just set (or reset) each flip-flop, put the combined bits onto the data bus through a 244, and trigger interrupts ...

Ok, hmm, even easier, then...

IRQ lines sit HIGH normally, feed them to a 3-to-8 encoder, which normally sits at the value of 7.

Feed the outputs of the 3-to-8 encoder to a 74HC374 octal D-latch as well as a 74HC10 (three input AND gate). Connect the output of the AND gate to the IRQ# of the 6502 ...

The 65816 (dunno about the latest 6502), has a "Vector Pull" line. Basically, it goes low during an ISR address fetch. So, could basically feed your 3 bit Interrupt number into a small EPROM along with the output of a flip-flop to select the low/high bytes of the word as needed. Or, if you don't ...

Mmm, good suggestion!

Tho, I was more wondering if my understanding of the timings given was correct.....

Hmmm, so I've been doing some thinking, and come up with a few questions.

I got some pointers on an earlier project (that I have yet to do anything about), as to how to work with some of the smaller CPLDs. So, I've been toying with the idea of using a CPLD coupled to a 74ACT715 video sync generator ...