Ummmm.. is it possible you subsequently made another mistake expressing yourself? I think I know what you mean, but it seems to differ from what you said. :|
No offense, but I don't see how this furthers the discussion... which, to me, seems very much in danger of going off into the weeds because ...

However, I think the idea of the three shifted clock signals is promising. Even though not using BE signal at all.

Let's have a look to the following timing diagram:

weena-timings.png

In the top block we have the three clock signals shifted 10ns each other. Please note I am using 12Mhz ...

Oh, nice catch! Yes, tBVD (be TO Valid Data) max is 25ns. This makes my proposal unfeasible.

Many thanks for the info!

I might be missing the point of what you're trying to achieve here. It sounds overly complicated compared to using an external tristate buffer and doing DMA during Phi1.
I am proposing a solution to the lead post in this thread.

The point is that the datasheet does not assure we can avoid data ...

Yep, my fault. I said RDY, but I meant BE (Bus Enable).

BE does not interrupt the CPU at all. It just makes the CPU to stop driving the address and data buffers. Once the memory controller latches the bank address after PHI2 rise, it could also deactivate BE. And hence ensure the data bus will be ...

I am quite late to the party. But I have a question.

Yes, it is clear that even using a transceiver in the data bus there could be contention. But, we have some ways to inhibit 65816 driving the bus, right? Would it be possible to use the
BE (Bus Enable) signal to prevent it to drive the data bus ...