George - how does your SLOWCLK circuit cope when there are two consecutive accesses to a slow address range? If I understand your comment above "Next is another ROM cycle - note that it waits for a fresh falling edge on the slow clock" this implies that you can't actually achieve consecutive slow ...

In the good old days there were a few accelerator boards for the Beeb - I had a 4Mhz one and it worked really well. They worked by removing the 6502 and replacing it with a board that had a faster 65C02 plus some glue logic that detected when the address being output was in the IO range and clock ...

Here's the "Circuit" emulation file for this.

I might have actually cracked this...

Ray

As previously mention on this thread I'm looking at a hypothetical "fast BBC micro" design. A key criterion is to be able to run the system VIA at a steady 1 MHz clock, because it's used as the system timer.

More by luck than judgment I've come up with the attached design, which appears to work in ...

Note also that pin 2 is sometimes an output - ideally you want to pull it high but not force it high. Alternatively if certain instructions (STP and WAI) are executed you need to dynamically switch it to being an input rather than an output.
Noted, but shouldn't be an issue without STP or WAI in ...

Nice work figuring out how to set this up in minipro, that's super useful.

The observations sound normal (e.g. the extra cycle, and the WDC 65C02 not executing the stack writes during the reset sequence).

One thing to be careful of is pin 1 - on the WDC 65C02 it is an output pin, not ground, so ...

This set of vectors is now working for my W65C02S. It seems to take a few more cycles than the R6502 before it reads the reset vector, and it never asserts write-enable.

EDIT: removed, because of the VPB held low issue - will repost once fixed.

I've been playing with minipro 0.7.4 under macOS, and here are my findings so far:

- the .xml file above needs to use a <logicic> rather than <infoic> outer block
- minipro refuses to parse the file if the chip's voltage isn't listed as 5V
- Pin 21 is not supported for GND on TL866A/CS

With a ...

This is very cool!

I shall have to try this out tomorrow under macOS, which is where I usually run the minipro open source programmer, built using MacPorts.

MacPorts is currently on 0.7.2, but the recently released 0.7.4 has much improved support for the later T56 programmer so I'll build that ...

I'm not sure I understand your remarks, Ray. You say no-one seems to generating the '816 bank address latching signal from a merely delayed PHI2 signal, but a delayed PHI2 signal *is* what's used in the diagram I posted . The delay of the 'AC02 is admittedly very short, of course. Can you be more ...

This seems like a promising place to start for my hypothetical '02 system to run like a fast BBC Micro.

This is very hypothetical, but the idea is a real 65C02 at 8MHz+, with a real 65C22 system VIA running at the original steady 1 MHz (it provides the MOS system timer) along with scope for other ...

Apparently the purpose of the inverters is to introduce some propagation delay comparable to that of the 'AC02. As a result, a rising edge on the 573's LE input will occur at virtually the same instant as a falling edge on the CPU's Phi2 input.
After poring through many threads on cycle timings ...

I'm puzzled by the memory map in his design.

He appears to be throwing away half of the 62256 32kB RAM to make space for the I/O, still leaving 32kB left over for ROM. :?

(strictly speaking, writes to the top half of the RAM chip's address space will still reach it, but you can't read them back ...