You can design a 6502 SBC without any glue logic and run it fairly fast at 14Mhz, viewtopic.php?f=4&t=6455&start=75#p114984

All valid reasons to go 4-layer, but once a design is simplified down to 100mmX100mm, 2-layer becomes easy to design, cheaper and faster to produce. Since 2017 when I became interested in retro computers, I cannot think of any my pcb designs bigger than 100mmX100mm. There were few among them that ...

Interesting thing about the VGA65 rev1 design is not only 6502 in DIP40 package, but the pc board is only 2-layer and autorouted without any attention to matching length nor minimizing the clock trace. My standard practice with 2-layer pc board is reduce the board size by 0.05” all around, autoroute ...

Does your CLK (32khz) ran fast? 32khz clock is very low power and sensitive to noise pickup, so there is an exclusive zone around the clock logic to shield from noise. Have you trace out the clock logic to make sure there are no fast signals running next to it?
Bill

Needing to press reset multiple times is troubling. I’m wondering whether there are mechanical intermittent contacts that are changed by the action of pressing reset button? Problem may have nothing to do with reset but rather the flexing of the circuit board.
Bill

I had a Z180 design that worked fine, made several copies, and had the design built and verified by others; a year or so later during an unrelated troubleshooting session, I discovered accidentally that Z180 power pin was never hooked up! It was entirely powered through protection diodes all these ...

Another example of stacked IC of different package. This is overclocked 6502 to 36Mhz. Started with CPLD at The bottom, then added PLCC44 6502, and finally SMT RAM on top, viewtopic.php?f=4&t=7433&hilit=Producti ... t=0#p97252

I wanted to reverse engineering this commercial MPU board from ADC Soneplex line, so I glue a CPLD on top of RAM array, glue a JTAG programming header on top of the CPLD. It was a tracer/breakpoint/debugger. After all that, I had abandoned the efforts to understand existing software and chosen to ...

5ns ROM would be nice to have, especially for fast 6502. I generally resort to CPLD or 22V10 for 10ns ROM, but their size is limited to 64-128 bytes.

CF interface is simple enough that you almost don’t need a ROM to bootstrap a computer from CF, almost. The initial wait for ‘not busy’ can be a deliberate pause after power on, followed by injection of read command, $20, into CFREG7, another short pause, then processor can read the data coming out ...

Ah, the joy of bringing up a new board. Sometimes it was so weird, I wondered whether basic laws of physics were altered! Building two boards is the logical diagnostic step, then visual inspection, then the simplest tests with fewest components. Don’t add, subtract, simplify instead. Check the heart ...

It turns out the top speed of VGA65 rev1 dropped to 33 MHz once CF is added. Except for the one wire wrapped outlier, all my other attempts that have 6502, RAM, CPLD, and CF maxed out around 32 or 33 MHz. Reducing bus loadings is the key to higher speed, but a reasonable computer needs memory, I/O ...

While checking out the design margin of rev1 VGA65, http://forum.6502.org/viewtopic.php?f=4&t=6517&start=30#p115070 I thought about the overclocking experiment so I changed the original VGA65 CPLD equations to that of the overclock platform. I also disconnected the CF disk to reduce data bus load ...

The salvaged EPM7064STC100 is 7nS part, faster than my stock of 10nS EPM7064SLC44. It occurs to me that this board may run quite a bit faster than 25.175MHz if I replace the 25nS RAM with 10nS. So I built up another board with 10nS RAM and reprogram the CPLD to be like CRC65. To reduce the data bus ...

Your multiplexed dot-matrix display reminds me of similar display I built up from individual 0603 LEDs and the associated CPLD to drive it. There are 6 digits in this homemade display, meant to display addresses and data on RC2014 bus. Each digit has 20 LEDs, so there are 20 row drivers. Since only ...