Motorola could have followed Intel to make faster versions: pipelining, single-cycle simple instructions…
They did actually get that far, at least. The 68040 and 68060 are roughly equivalent to the 486 and Pentium Classic respectively, having similar architectures with in-order pipelined and, in ...

Appreciating that not every pet architecture can be stuffed into a single poll, here's my assessment of the options provided:

6502 & 65816 were never really intended to be easy for humans to work with. They're simple enough that doing so is tractable, but you need a lot of experience to make the ...

Not sure. I was something like 5 or 6 at the time, so…

Hence my slightly more robust option of replacing a <= b with NOT(a > b).

Bil Herd summarizes the situation. “No chip worked the first time,” he states emphatically. “No chip. It took seven or nine revs [revisions], or if someone was real good they would get it in five or six.”
The ARM1 must be the exception that proves the rule. It did work first time - the ...

From my own design, I can see how mandatory LET could simplify the code, since it reduces the things you need to recognise at the start of a statement - you're always looking for a keyword, which is in the keyword table, and if it's LET or FOR then the next token is a variable name. Without ...

It looks like you're using Knuth's sequence for Shellsort. While it's definitely not the worst one out there, I've found a couple of significantly better ones that are also quite easy to generate.

First is a Modified Sedgewick sequence, essentially 4^k + 3*2^(k-1) + 1 but continued beyond k=1:
405 ...

At 4.5V, the 'HC573 requires an 8ns hold time at room temperature and a 10ns hold time over "industrial" temperature ranges, which are both met by the '816 running at 5V - but only just. You would need to take a lot of care over the skew between the complementary clocks being provided to the CPU and ...

More precisely:

The B bit in the status register does not actually exist, and always appears to be set when pushed using PHP. It is not affected by any value loaded using PLP or RTI. The same goes for the unnamed bit next to it. The status register really has only 6 bits in it, and only one or two ...

Wouldn't it be simpler to just connect the reset signal to the D input, and then make sure you have an appropriate polarity of clock to the flipflop?

The flag bits are mostly NOT initialised on reset. The exceptions are that interrupts start out masked (because Reset is treated as a special kind of interrupt, and all interrupts mask further interrupts), and on CMOS versions the D flag is also cleared - but on NMOS the D flag is NOT initialised ...

Synchronise the reset signal with a clocked flipflop?

This is much better:
Mandelbrot2.png
0 S=4096
5 T=S*4
10 A=S*-21/10
20 B=S*3/2
30 C=S*3/2
40 D=S*-3/2
50 E=200
60 F=(B-A)/128
70 G=(C-D)/48
80 L=C
90 REPEAT
100 K=A
110 REPEAT
120 V=L
130 U=K
150 O=-1
160 REPEAT
170 Z=(U*U-V*V)/S
190 V=U*V/(S/2)+L
200 U=Z+K
210 O=O+1
220 ...

I have a suspicion that those aren't really overflows, but might be due to a subtle bug in the interpreter which would only show up with large-magnitude numbers. The near-threshold iterates in those regions should not be overflowing 32 bits with the scale factor I've selected, but might overflow 24 ...

And, what I'm sure you've all been waiting for:
Mandelbrot.png
0 S=2048
10 A=S*-21/10
20 B=S*3/2
30 C=S*3/2
40 D=S*-3/2
50 E=200
60 F=(B-A)/128
70 G=(C-D)/48
80 L=C
90 REPEAT
100 K=A
110 REPEAT
120 V=0
130 U=0
150 O=0
160 REPEAT
170 X=U*U/S
180 Y=V*V/S
190 V=U*V/(S/2)+L
200 U=X ...