Just in case anyone finds this and has the same questions - I thought I'd add that the audio generation is in fact simply some resistors. Or at least, I'm assuming this is a resistor chain DAC each with 4-bits of precision. The video makes sense logically to me after the explanations here, but I ...

Thank you all!

I'll continue to investigate and see if I can't figure out what the VIC (or NES, even) does specifically, but some of this information is really great to help direct me in understanding how the signal could be formed. I'll also try building a little play circuit to see if I can't ...

Hey All,

Recently I bought an oscilloscope and measured the NTSC signal pumping out of an NES' composite video output. It was an interesting experiment, and the thing that really surprised me is how clean the colour burst and associated colour signals were. I half expected something blocky but ...

Thanks for the feedback! :)

The interrupt registers idea is pretty cool, and I hadn't considered such a setup; do any chips actually do this?
I'll keep it in mind, but probably won't implement it in this design (for a number of reasons).
However, I have thought about this more and I've decided I'll ...

I decided I'm sticking with the name "base-page", for one it seems to me like a natural naming evolution from "zero-page", but also I found in the 65CE02 datasheets they actually refer to this style of addressing mode as "base-page" as well! ( http://archive.6502.org/datasheets/mos_65ce02_mpu.pdf ...

(Note: I will think about the naming here before making the change, but for now I will call it "base-page addressing mode" to keep things sensible in this discussion.)

This change would modify all existing "zero-page" like addressing modes to be "base-page" like (perhaps I wasn't clear in ...

Thanks BigEd!

Next weekend, I think I'm going to make the following changes to my ISA and then call it done:

1. Rename SBB -> SBC and double-down on the carry/not-borrow bit.

2. To heck with the ISA encoding scheme, I'll add LDB/STB/TAB/TBA/PHB/PLB in some of the free instruction slots I have ...

About Decode ROM:
Thanks BigEd! That is very interesting, provides a lot of context I was missing in understanding the clock speed range of the 6502. I think in the case of my fantasy CPU, I'll play clock speed by ear and allow this to be one of the places I take more liberties with the design. It ...

Thanks for the discussion and encouragement everyone! :)

About the decode ROM organisation: I think different organisations are all valid, it might be better for understanding and debugging to do it one way rather than another. Or it might be better for maintainability, or for implementation. But ...

Hey Everyone!

So I've been working on a project to understand microprocessors a little better, it's been a great educational experience, and I have learned a lot especially from here (and the visual6502 simulation, of course). I am basically designing a CPU based almost entirely on the hardware of ...

Yeah, I wouldn't mind taking a stab at writing a wiki page on this - it might take me some time though. I'm still learning things about the 6502, and I only get time to really look at this stuff on the weekend in any kind of depth. I'll take a look at doing this over the next week or two. I also don ...

Thanks, everyone! This is all really useful information.

Taking what you all have said into account, I'm watching the AB1 pin and I can see some of the engineering you were discussing at work here - specifically, I think I see how the pin being low or high allows current to flow to either dissipate ...

So, I'm having trouble understanding what "Precharge MOSFETs" means from the block diagram ( https://projects.ncsu.edu/wcae/WCAE1/hanson.pdf ).

I'm trying to understand physically how the 6502 handles a BRK instruction. I get how it works logically, but I'm confused about how it orchestrates things ...

Thanks BigEd!

Thanks BigEd!

So it is as I thought, I appreciate the confirmations on this. I won't do anything more unless it is asked of me here, but my 2 cents is that it'd be clearer - especially given the case where some RMW operations waste a cycle - to display the ADL/ABL and ADH/ABH as DPC signals ...