DRAM refresh cycles are driven by the VIC-II in the C64. It's the basis for the arrangement. The CPU runs at half the speed of the memory in order to let memory access appear instantanous. This saves circuitry for arbitration. I still think it's a bad idea that the VIC can steal memory cycles from ...

ARM was very expensive. Double bus width => double price of the borard, the pheripherials the chip package. It even has 4 times the bus width. Then while I do math stuff from time to time, people like text. Text is byte based. 7 bit was never enough, 16 bit did not survive gloablization, utf-8 ...

I want to avoid Duff's Device and I think on (my design so far but genereally before 1980) there was an imbalance between registers. Let's assume that the highest byte of the counters will be implemented a bit for a year. Apple ][ gets none, C64 one, C128 two then up to 8. But anyway about 16 bytes ...

Took me one day to get of my branching thoughts. One (additionally) MIPS like
loop with loop length within the byte
last operation of the loop (no influence on jump condidtion)

Another day (on and off) to follow all the links: And I have to say am not interested in a widebus variant. I like bigger ...

gotta go to work soon, but:

@BigEd
I think no thread was much more specific to my topic than any one else. I think I googled about this for some time. Will have a look at it.

@GARTHWILSON
Goal: mute all this discussion: "I want more regs". No you can't. Also I wanted to understand modern CPUs. For ...

I looked at that RCA CPU also and on both CPUs I cannot see much bloat that could be reduced. Okay the 6502 opcodes seem to have been layed out randomly. When I first read about RISC it was about cache and being able to specify 3 regs in one opcode. And like on a 486 years later, every instruction ...