Just getting back to this after a year.

I had put together some test code to generate tones from Timer 1 toggling PB7. Physically, I routed this through a reproduction of the Apple II darlington-based driver circuit.

It's funny how a year changes things. Fresher eyes found a couple of typos e.g ...

@Mike: looking at your edited post with the PCB layout, it looks you're breaking the other RC2014 rule: no fancy modern ICs like that PIC :)

For folks who don't want to layout/design your own 6502 boards for the RC2014, I got 10 more of my RevB boards in on Tindie.

The main differences of Rev B ...

I realized after looking at 6522 timer example code (e.g. on Jeff Tranter's website) that I'd used the wrong values for a 10ms tick. It looks like the actual value to use for the timers is 2 less that the calculated one. So for a 1MHz system I needed to use 9998 instead of 10000 for 10ms. The ...

@Michael: nice! Is that the Kicad feature that allows you to show the board in 3d?

Be careful that the VCC line between VCC and /RST is actually not VCC but the Z80 /M1 signal. This signal is needed to qualify I/O ops vs interrupt ack. I tie that to high/VCC on my non-Z80 CPU boards.

I generally ...

I'm curious about this, though. Is gating with /MREQ unnecessary strictly because the I/O page is hard-wired to be in the upper half of memory? I'm thinking of putting the 74688 for the I/O select on a standoff and changing the wiring to relocate it to $0200 instead, so that might not work in that ...

To make it simple, use two 32KB RAM chips.

Since you are using your own memory design, you can choose to connect pins 1-2 of the A15 option header. This will give you the raw A15 with no inversion.

The lower 32KB can be enabled with A15=0. You don't need to gate it with the /MREQ signal of the ...

(Also, have you run this at higher clock rates? Any idea what the highest stable frequency for it is?)


So I got around to mucking around with the Western Design Center W65C02 which is rated at 14MHz.

Guess what...

It didn't work. Well, the monitor/debugger started out and then printed rubbish ...

The discussion is probably moot at this point because the W65C22N6TPG–14 is no longer available at Mouser. Or at least, it's backordered. On the other hand, there's plenty of the 's' version...

I was in the process of putting up my spare boards on Tindie and writing up a recommendation for 6522 ...

For the other benefits, I would still recommend the S version.

That's funny. It sounds like there's some history/politics behind this endorsement :?

Since the RC2014 is a hobbyist system, I'd recommend that folks use what they have at hand, especially if they want to recreate the retro vibe of ...

Tested with a WDC 65C22N this morning.

6522-wdc-small.jpg

I've also update GitHub with the latest code with interrupt handling ( https://github.com/ancientcomputing/rc2014/tree/master/source/6502/6522 ).

The code show how you can chain interrupt handlers: 6522 timer 1 interrupt chains to the ...

The RC2014 design only has one interrupt line (other than NMI if you have the Pro motherboard with Enhanced bus).

So the assumption is the use of open collector/drain devices to share and drive that interrupt line. My Rev B & C 16550 board designs use a 74HCT03 open collector gate to convert the ...

Yes it is. That's the next level of testing. I'll need to chain interrupts with the serial console. Fun stuff!!

The board files have been checked into GitHub: https://github.com/ancientcomputing/rc2 ... 6522_board

I spent most of this beautiful Sunday afternoon cloistered indoors and working on bringing up the new 6522 VIA board for the RC2014.

6522board-small.jpg

It is set up as a typical RC2014 board except for the use of the R/W signal on pin 39 of the RC2014 bus. I decided not to use the /WR signal ...

I've added the 65xxx.lbr Eagle library to GitHub: https://github.com/ancientcomputing/rc2 ... /eagle/lbr

I downloaded the original version from diymodules.org and added the 6532 component. I have a 6504 lying around. I'll probably add that next

BigEd has a point that a lot of modern FTDI-style interfaces don't stop the flow immediately on RTS deassertion. With an autoflow control capable 16C550, I have the watermark at 50% (8 characters). The code that I put together yesterday uses a 1/3-2/3 low/high watermark.

Proper design is key here ...