I tried the Klaus Dormann test again in the Xilinx ISIM simulator, this time without a waveform database, but it was still taking too long, so I ran it on the Spartan 3E Starter Kit and I am happy to say that it passes.

Ed, I have run the AllSuiteA test to completion in simulation; and I have run the Klaus Dormann test in simulation; however, it reached the size limit of the waveform capture file and halted prematurely after some hours. I need to re-run it with maybe just the program counter being logged. I have ...

Arlet, thank you. Are you Arlet Ottens, the author of https://github.com/Arlet/verilog-6502 ? I tried your core with my Pool demo. It dropped-in very easily. I managed to close timing on it at 50 MHz, no problem, in a Spartan 3. It is very economical on FPGA resources.

Ed, as you probably know, the ...

Hello All,

I am new to 6502.org and would like to introduce myself. I am a lifelong electronics and software hobbyist and a professional electronics engineer. I recently auto-generated a Verilog 6502 core from the Visual 6502 transistor-level net list. Documentation and full source code can be ...