I have been wanting to work on a 32 bit version of an FPGA based 6502, but have been a bit unsure exactly how far to go. Here are my thoughts:
1. Revamp the whole addressing scheme - see below
2. Add only minimal instructions to the 65Org16 set - a 32X32 bit multiply and 64/32 divide would be what I ...

Arlet,

100MHz is surely flying. I am going to get started on hooking this up to some of Grant Searle's Multicomp peripherals on my Terasic DE1 board and see what happens. I figure I will start out with a cpu clock of 5MHz or so just to get things working and see where it can go from there.

Arlet,
Thanks for the clarification. Does your core output the same type of address nonsense that the 6502 did during internal cycles?


I have examined the RTL and the detailed fitter report and it appears that the optimizer elected to make a wide "or" gate component into a ROM lookup table instead ...

Ed,
Thanks. I am somewhat flabbergasted the core is so small. I downloaded a cycle accurate 65c02 and the thing takes about 4500 LEs on the Altera device. I guess one doesn't need many resources if total compatibility is not required.

Also, what is the status of the full 32 bit version (65Org32 or ...

I am interested in using the 65Org16 core and got the Verilog source from Big Ed's GitHub page. I have compiled it for an Altera EP2C20F484C7 FPGA and the flow summary shows that only 690 cells and 2304 bits of ram have been used. This seems VERY light to me. Have I got the correct files?