As predicted the problem was so simple, I must hang my head in shame. OE on the SRAM was left floating, which created very subtle data bus contention, making it look like things were working but actually were not.

In happier news there seems to be a wealth of the R65C51 floating about on eBay at ...

What does your routine to set up the '51 look like?


Here is the full code for the test program.


.segment "OS"

ACIADATA = $5000
ACIACONTROL = $5003
ACIACOMMAND = $5002
ACIASTATUS = $5001
VIACONTROLA = $6002
VIACONTROLB = $6003
VIADATAA = $6000
VIADATAB = $6001

NMI_VEC
IRQ_VEC ...

I've tried one more experiment, but this may be invalidated if my interpretation of the datasheet is wrong. The block diagram shows there being a separate Transmit Data Register (TDR) and Receive Data Register (RDR), so i have made an assumption that reading from the 65c51 will be pulled from the ...

Welcome, chrisabird :)

Which get's it stuck in a never ending loop waiting for data, as the receive bit is never set.
Is the wiring new? It may be that, due to a wiring error, the bit you're testing actually isn't the receive bit -- which would explain why it doesn't behave as expected. For ...

Thanks all, lots for me to consider, back to the bench with some new angles to try! Report back shortly

Chris

I'm down to my last ounce of patients with this chip, but stubbornness stops me for giving in...

So i'm trying to get the following to work...

USB ----> CP2102 ----(Rx,Tx,DTR)----> 65C51

This is working fine for receiving from the 65C51 (after a skirmish with the Xmit bit issues) but i just ...