I used the LVC244 to down shift 5v from a Z80 to a cyclone II FPGA.

Going the other way used an HCT245 with the direction locked because that was what I had in stock. The HCT244 would have been just as good.

Both parts are through hole, easier for prototyping.

Have you remembered to reverse the data bus?

TI documents of the era consider D0 to be most significant. Which is the opposite of how the 6502 etc define things.

Meaning CPU D0 goes to VDP CD7 on pin 17, etc round to D7 connecting to CD0 on pin 24.

Time for some examples I guess.

http://forum.6502.org/viewtopic.php?f=3&t=5728 It the write up of the Atom build I did, you'll note from the first board there's an Alliance AS6C62256 32k ram on there with an older 10MHz W65C02. The date code of the ram isn't clear, but it's 1127.

I've put the ...

My "Solution" was to use alliance memory chips and interpolate for the blank spot on the datasheet! They're CMOS devices themselves, with a wide voltage range, they're not going to have the limited drive of TTL.

If the drivers can output a guaranteed 2.4v** from a 2.7v supply, and typically do 3v ...

You could try replacing
FIELD Address = [A15..5];
in the second attempt with FIELD Address = [A15..0];
Even though A0 to A4 aren't connected, they're part of the 16 bit address. As long as the addresses ranges resolve to don't care for the low 5 bits WinCUPL should be happy.

This code from my ...

I generally define some locations in zero page for "throw away" pointers and such. With labels like tempW1 or tempB3 to make it clear what they are.

They're purely used for here and now actions so it doesn't matter if they're over-written by subroutine calls. Anything needing more permanence than ...

The main problem for a binary resistor DAC is finding resistor values that are exact powers of two, i.e. 1K, 2K, 4K, 8K, etc..
For a 3 bit DAC, exact powers of 2 are easy, as long as you have the middle value resisrtor to hand.

2 resistors in parallel will give you half the value.
2 reistors in ...

Have you tried another monitor, just in case it's "Fussy" that's clipping the display ?

The VIH figure from the DC part of the datasheet shows you the minimum voltage that will be accepted as a high, in this case that's 2.0v. There's no maximum quoted so anything from 2v to the absolute maximum of any pin of VDD+0.5 is acceptable. (Though input voltages over the supply should be ...

the main reason the ROM is so large in the first place is to allow in-system programming, as that requires having control over atleast the bottom 15 Address lines of the Flash.

If you're not bringing out CB1 and CB2, could you use CB2 for A14 to the ROM?

That would allow you to shrink it to 16k ...

If you need to drive the address lines, rather than using pull ups, you could add a 74xx157.

If you feed A15-A18 to both input banks of the with select pin tied off high or low. With *access feeding the enable pin, the 157 will output all lows when the enable is high and the fixed 4k is in use, and ...

The Propeller P8X32A is not 5V tolerant so voltage-level translation is definitely needed to interface it into a 5V circuit.

There's a note on the P8X32A datasheet that says: "I/O pin voltages with respect to Vss may be exceeded if internal protection diode forward bias current is not exceeded ...

It might be interesting to look up how the Apple 1, the PET, the Superboard, the Atom managed their reset lines - I expect they were pretty minimal about the arrangement. Even moving forward, to the Apple II, the C64, the Beeb, I wouldn't expect to see a reset controller - maybe a monostable.

I ...

you can always try soemthing like: Which should set pinx high.

I am confused. I have just started working on a 65816 design, so I am pretty much a newbie here. Doesn't the CPU output the bank address on the data bus during phi2 low phase? I thought it wasn't possible to share the bus on a 65816 system, as we do with the 6502.
That's not a problem if the CPLD ...