this is my first attempt at this. Looks like you've got a good grasp of the subject, yvibod. :) But it may be your circuit is more complex than necessary.

Goal is to divide the address space in 8 chunks of 8k, and the first and last chunks into 4 2k each.
And your circuit maps the six 8k chunks ...

I believe this is what yvibod is trying to describe

sch.jpg

Wow, thank you for taking the time!

Here are the schematics on the chips:

ROM:
http://forum.6502.org/images/migrated/040869-000.png
http://forum.6502.org/images/migrated/040869-001.png

RAM:
http://forum.6502.org/images/migrated ...

Hello! If you guys could help me go through my memory decoding scheme to make sure I haven't done anything wrong that would be greatly appreciated :D
Chips:
3 - 2k ROM
3 - 2k RAM
1 - 6522 VIA
1 - 74LS139 2 to 4 decoder (two on the dip)
1 - 74LS138 3 to 8 decoder

Goal is to divide the address ...

Ah I see now. Thanks, that makes sense.

Ah, that's more like it! So, indeed, having decoded down to 8k blocks, you need to decode two more address bits to get to a 2k size. There is such a thing as a 2-to-4 decoder, or you could use some NAND or NOR gates probably.
Edit: or indeed use another 3 to 8 decoder, if that's what you have, and ...

Sorry, it's actually 2K. It's a HM6116P for RAM and a XLS28C16BP for ROM

You'll want the RAM contiguous so programs don't don't have to jump over dead or mirrored spaces, and so you can have contiguous data arrays. Why not just spend a few dollars on a 32Kx8 SRAM? It will pay for itself in the reduced number of sockets required, the labor to wire-wrap it all, and in ...

Welcome, yvibod! With a single 3 to 8 decoder you can split the 64k address space into 8 sections of 8k each. You have 7 devices to fit in, so if all the devices are 8k or smaller, you're already finished!

As BDD notes, more information is needed to solve the problem. But to answer your question ...

Welcome, yvibod! With a single 3 to 8 decoder you can split the 64k address space into 8 sections of 8k each. You have 7 devices to fit in, so if all the devices are 8k or smaller, you're already finished!

As BDD notes, more information is needed to solve the problem. But to answer your question ...

Thank you for the suggestions, the chips are 3 RAMs of 3K each at the beginning of address space, 3 ROMs of 3K each at the end and a VIA at the beginning of the second 32K bank. Before I made the question I was looking for at tool that would do this sort of work but now I tried doing it by hand it ...

Hello, on my first 6502 project i have to divide the address space between 3 RAM chips, 3 ROM chips and a VIA. I know how this works, but i was just wondering if there is any tool available or formula of some kind to help me do this the most efficient way possible? I plan on using some 3 to 8 memory ...