Ah, I see they also make a 16550 variant as well. QFP is no big deal. I didn't realize the 450 only had a single byte buffer - thanks a lot for the tip!

Hey all,

I came across this little chip on mouser.com today, just casually looking for an ACIA alternative, not that I'm terribly unhappy with it or anything, but I might've found something interesting - it's a dual UART in a "friendly" PDIP package.

Exar ST16C245 and Datasheet

Dual channel, 8 ...

Thanks to you both - I've now got my AVR-based PS/2 decoder talking to the serial lines of the 6522 and am displaying text on the screen! Cheers.

Thanks Garth. I got my CB1/CB2 input problem solved - I miswired my DB15 connector that I'm using for Port B :-/.

Anyway, now that I've got the right inputs going into CB1/CB2 with the 7474 on the input clock, I couldn't get the 6522 to fire an interrupt. I was sure that I initialized everything. I ...

Hey all, Happy Holidays to you all.

I'm trying to set up the 6522 for serial operation and I had a question about the CB1 and CB2 lines. It looks like the clock line is active low, but on reset, it looks like both CB1 and CB2 are low - is this normal?

Here's roughly my reset logic for the VIA ...

Thanks all for the input. I decided to go with the following, I think it's an improvement and a good compromise.

Text Mode (8x8 font at 640 x 200 operating in 640 x 480 @ 60Hz timings)
Previously, the FPGA would naively prefetch the next character byte, the next color attribute byte, and the 8x8 ...

Thanks cr1901 for the CGA documentation! This will be interesting to compare against my pseudo-CGA implementation in Verilog.

I looked at that PDF a little bit and it looks a lot how my address generator and simple DAC works. The 6845 is the real mystery to me I think, so I started looking at that ...

Reading or writing the video RAM was accomplished by setting an address in a pair of registers, using the control register to tell the VDC which registers were to be set, next telling the VDC that the data register is to be selected, again by writing to the control port, and then reading from or ...

Is shared VRAM a hard requirement?
Not at all. It seemed like a pretty simple hardware-based approach with minimal Verilog changes, though.

If I were doing this project, I'd probably wouldn't share VRAM between CPU and the videpo controller. I'd do something similar to the Sega Genesis VDP ...

I'd go with AppleII bus sharing if possible. How fast can the 65C02 run ? Could you interleave the video access with the 65c02's access by providing a clock from the video subsystem ?
For instance, the video byte data is required at 1/4 the pixel clock rate or about 6MHz. If the C02 could run at ...

Hi all,

I'm working on the video portion of my homebrew computer project. I've already implemented a CGA "video card" in FPGA which interfaces directly with a 16K SRAM window and a 8K font ROM. My problem: how to share this 16K VRAM with the CPU. If you're not familiar with CGA, it basically boils ...

Hi all - my first post here! :)

I wanted to share some information regarding EAR classification of some WDC 65Cxx parts on mouser.com. I recently tried to order the following parts:

955-W65C816S6PG-14
955-W65C51N6TPG-14
955-W65C22S6TPG-14
955-W65C02S6TPG-14

Some of you might know that Mouser ...