Looking back at the OP's schematic, he's using the 74HC138 chip select output to drive negative chip selects for both the 65C22 and the RAM chip, which is normal. He's also using the same 74HC138 chip select outputs via a 74HC10 gate section with all inputs tied together to form an inverter to ...

I left pin 4 of the '138 floating. Is that bad?

So I just tried reinstalling each chip one at a time. Everything worked (chip select lines, address bus, etc. matches what was expected) until I installed the VIA. Running it with just the glue logic, CPU, RAM, and both ROMs works. When the VIA is installed, everything stops working. Since the test ...

Alright, I just built the NOP generator and tried it out. Everything seemed to be working. I used a buzzer to measure the frequencies of certain pins as suggested on Lee Davidson's NOP generator page and I heard what he described - the frequency of the sound got higher as I went down from A15, and ...

I'm using ACME version 0.91.

This is the test code:


; Register definitions

VIA_PORTB = $FE10
VIA_PORTA = $FE11
VIA_DDRB = $FE12
VIA_DDRA = $FE13
VIA_T1C_L = $FE14
VIA_T1C_H = $FE15
VIA_T1L_L = $FE16
VIA_T1L_H = $FE17
VIA_T2C_L = $FE18
VIA_T2C_H = $FE19
VIA_SR = $FE1A
VIA_ACR = $FE1B
VIA_PCR = $FE1C
VIA_IFR = $FE1D
VIA_IER ...

I did notice there is no apparent pull-up resistor on the processor NMI line, nor is there a dedicated one for Reset. Is your circuit on a PCB, wirewrap board or breadboard? Are you using adequate decoupling caps at each of the chips? Agreed that a detailed memory map would be a plus.
I built it ...

I converted the schematics to black and white. Apologies for the confusing layout - I hope they're a bit easier to follow now.

I'm using all 74HC logic, actually. I must have forgotten to change the labels from Kicad's defaults... :facepalm:

That NOP generator looks interesting. I'll give it a ...

Hello!

Background/info:

I designed a little 65c02 single board computer as a summer project. I finally got it built over the past weekend, and it doesn't seem to be working at all.

Schematics
Code

; Register definitions

VIA_PORTB = $FE10
VIA_PORTA = $FE11
VIA_DDRB = $FE12
VIA_DDRA = $FE13 ...

Almost. I've been pretty busy with schoolwork over the past week, but I'll upload them after I finish the clock signal generator.
Is Eeschema format okay?

Okay. I'm about 70% done with the new schematic, I'll upload it in a bit.

It's a SPDT switch, shared between PHI2 and a button connected to ground. I'll try disconnecting the switch and directly connecting PHI2 to the OE and CE lines of the RAM.

Just tried the 74HC14. Works possibly a little better, but still conks out when I wait longer than a few seconds between cycles.

Okay, I'll give that a shot. Would a 74HC14 work?

Seems that the data LEDs were causing some of the zeroing problems. Now it's back to where it was before.
The random jumping seems to go away if I speed through cycles. If I only end up using the board at 1MHz (my master plan), will this issue be worth fixing?