BDD, thanks for the appreciation/compassion and the kind words.
To me, it is helpful to keep going, times are not easy for me right now.

Greyish-white wire.
Remembers me back to that day during apprenticeship, when I had to do a cable harness.
It started with placing a drawing on a piece of wood ...

Just one small nitpick - R_IFR (not W_IFR) should be connected to the readout of D7io.
Dang. Fixed this.
In my defense, I have to say that my head is full of 6561, and that it's getting increasingly difficult for me to stay focused/concentrated.

This reminds me that KiCad probably still doesn't ...

Dang: 10b)
In the schematics, it's low_active INT_ACT#, and that's correct.
In the chip pictures, that signal is labeled INT_ACT, high_active, and that's not correct. Fixed this. :roll:

Just for you, a quick drawing made from your 6526 ICR guesswork:

6526_icr.png

Dead Bird Eagle 6.4 schematic ...

Hi Dag,

I have just finished a MOS 8521 FPGA implementation based on your excellent work - kudos to you!
See https://github.com/daglem/reDIP-CIA
Thanks for the kind words.
It's always nice for us to see somebody putting our work to good use. :)

Here are a few comments / corrections which you ...

Thanks Orac81, we are aware of this thread.

Now for an update on the current situation:
The job at that obscure small company I mentioned is delayed due to a lack of funding.
My next temporary working contract at the university will maybe last 6 months due to a lack of funding.
Working conditions ...

Bitsavers:
AN-0815_Color_Graphics_For_The_MC68000_Using_The_MC6847.pdf

Not related to your question, but looks interesting nonetheless:
Retrocomputing Stack Exchange:
How did the Dragon modify 6847 video output timing for PAL?

Friends, thanks for the condolences and the compassion.
This helps.

My father was quite active util the stroke. He died at age 87.
And the work he did in the house + garden now became my work...

News update for October 2025:

My father had a severe stroke in July, and died after two weeks in hospital.
The paperwork caused by his death kept me busy for 3 months.

But at least now I recovered from the failed WD1772-02 dissection.

Took a look at some part of the SSI263AP / Votrax SC-02 speech ...

Thanks, Ed.

The problem with logic level FETs is, that they have more capacitance than bipolar transistors,
what limits the speed.

That's all so far.
You are on your own.
Good luck.

pla.sch, pla.brd

It's rather big. Note that a 6502 would require 10 such modules.

+3.3V supply, CTL AND based PLA with 22 (buffered) inputs and 15 outputs.

Pulldown resistors at the CTL gate outputs are not included,
because you may want to build big AND/OR combination gates by creatively ...

stackpointer.sch, stackpointer.brd //one Bit.

+3.3V supply.

Two CTL outputs with enable.

Pulldown resistors at the CTL gate outputs are not included, because you might want to connect them to bus lines.

nand.sch, nand.brd

+3.3V supply.

BSV52 based TTL NAND, open collector output with pullup resistor.
2 inputs, expandable with external PNP transistors.

driver.sch, driver.brd

+5V supply, when being creative 4 modules can be stacked, one inverting driver with high_active output enable.

Note that building (relatively) fast drivers which can handle capacitive loads requires "some black magic",
do don't expect this schematic to really work without ...

buf2.sch, buf2.brd

+3.3V supply.

Two CTL buffers, pulldown resistors at the outputs not included.
Thing is, that the outputs can be wired together for forming an OR gate.