I already had the circuit for the /PC generator, but I got it wrong. As the 6510 seems to do a read just before a write (I guess this also happens with the 6502, and probably the 65816, that's something I need to investigate) it was making my circuit to generate to separate pulses, instead of a 2 ...

Thanks for the info. I looked at the 74CBDT3861 level shifters as well. The TSSOP is the smallest footprint they make. You can see from the MockA65 schematic that every pin of the mock CPU has one level shifter (even VCC and GND???) along with a 10K pull-up resistor to +5V for all 40 CPU pins. The ...

I am a little confused! I thought you were this project: https://hackaday.io/project/165624-mocka65xx-universal-650285xx-cpu-replacement

I looked at your board layout from a few pages back and it's obviously not this one! There are two of you doing the same FPGA thing?!?! Your board looks like it ...

I would like to have some flexibility here to have some write-through caching. Hmm, at what level would you do the caching? Not the low-level disk I/O addresses, I assume. And even the RWTS sector buffer is not likely to see a write-and-read-back-immediately pattern all that often, I'd think.
Are ...

I want to switch to the 200MHz PIC32 which has 512K of RAM available. This would allow switching of ROMs on the fly, as well as having a large cache. I am not thrilled with MIPS assembly, and the CPU itself has some caching quirks you have to work around. For me, assembly is the only way to go as I ...

Probably a software emulation could sync its external bus cycles to Phi0 quite easily. As long as you operate from fast internal RAM, you don't care about Phi0/Phi2 anyway. When you encounter an address which requires an external bus cycle, you have all the time (and processing power) you need to ...

Yes, that link is valid (although I must admit that I forgot about it, and the design shown is quite dated). I have been kind of quiet about this and super busy since the world was up-ended by the pandemic.

Some answers to your questions: about PHIO - the 65xxT can either use PHI0 or become PHI0 ...

The memory mapping issue is a tough one. I ended up using a 4K of RAM as a map that represents 16 byte controllable windows for my solution (not FPGA, and only about 48MHz). You can define any of these 16 byte regions as fast or slow (accelerated or cycle exact). It's programmable via a serial port ...

I looked at doing something similar to what you are proposing, and then I explored the option to use just a fast microcontroller to completely emulate the 6502 itself and that is what I stuck with. It's small, cheap, and works. When running code out of the cache or internally mapped memory I can ...

I agree. There needs to be some type of benchmark really for the various instructions. This could be built into an instruction test program. Each instruction emulation takes a certain amount of time, and some optimize better than others.

Commodore 8 bit used 256 byte sectors. The Amiga used 512 byte sectors.

Someone already wrote a 6502 emulator (with BASIC and such) for the ESP8266. It should just compile for the ESP32. Check the actual Arduino forums for info on it.

I am more impressed that it generates a good video signal with that rats nest of wires! It's difficult enough to get a clean NTSC composite video signal with a dedicated PCB circuit!

The source code for DOOM is readily available. You can look at exactly how the pixel map is converted and push to the video hardware.

I spent 20 years of my life (permanent day job) writing software and designing hardware for the Commodore line of computers. Games didn't redraw the same data over and over again at 50/60Hz. That is myth that I had never even heard of before until this thread. There is a video buffer that is pointed ...