Well it’s been nearly two years since my last post on the forum: 31 May 2023. Very glad to see that that forum is still going strong. Three grandchildren, a heavier workload, and a 11 month Executive MBA in 2024 interrupted my participation on the forum. Glad to see many of the same names still ...

Although I haven’t contributed anything meaningful to the forum regarding my 6502-related activities in quite some time, I check the site frequently. Often learn something that I can apply in my day job; that is a concrete benefit to me and others here.

I hope to continue this learning process, and ...

Although I’ve not tried it with the 22V10 PALs, I did try it with the Coolrunner II CPLD family. I was surprised at how much of my soft-core’s microcode could be packed into these devices. The Coolrunner II parts are more like Programmable Logic Arrays (PLA) than the 22V10, but either part can ...

Second BDD’s response. Although my enhanced soft-core is not in a working state at the moment, I too included a full set of these type of stack-relative instructions in its instruction set. I also included a base-pointer relative mode, where I use X loaded with the value of S at the start of the ...

The operation of the carry flag in the 6502 architecture is like an active low borrow flag. In other words, when the carry is 0, a borrow has occurred.

The operation of the SBC instruction is: A = A + ~M + C. In other words, the contents of the accumulator are added to the 1's complement (bit wise ...

Well I haven't posted here on 6502.org often in the past few years. As a consequence I lost my post.

I think you'd have to classify the PIC16 family as a "Turing Complete" instruction set architecture. Therefore, although it could be wildly inefficient, I would think that there is an implementation ...

Actually, one of my favorite examples of a language using threaded code for its execution is the original compiler for DEC FORTRAN for the PDP 11/20.

Never mind. The application note that I was thinking applied to the Bell 202 modem instead applies to the Bell 212A/V.22 modem. It is a good backgrounder on the elements / modules needed for a modem, but the modulation scheme is Differential Phase Shift Keying (DPSK), and not the Frequency Shift ...

I don’t have access to the document at the moment, but IIRC, Texas Instruments wrote a very detailed application note on implementation of a Bell 202 modem with one of their DSPs. It described all of the modules required in detail, especially clock recovery. Maybe such a recipe may help your efforts ...

I think Ed's comment about the software vs. hardware view of the process is on target. The sentence in question causes some confusion by not identifying that the second and third bytes must be held in internal registers / latches that are not visible to the programmer. It is from these internal ...

Thanks John for providing the link. I enjoyed it very much. Congratulations to mysterymath and the team. I look forward for future updates and talks.

MicroCoreLabs' suggestion has merit. Furthermore, the implementation of the 8086 microcode in 6502 assembler can be optimized after initial implementation and validation of the simulation to improve the simulation speed.

For prefix bytes, cascade into a separate tree of instruction decode. This requires one root table of 256 cases plus one additional table for every prefix. I implemented my M65C02A soft-core processor extensions using prefix instructions, and I only maintain a single root table for all of the ...

When programming in assembly language, or perhaps using a non-recursive descent compiler without too much intelligence, it's fairly easy to set up the evaluation order of the operands for instructions like CMP and SUB/SBC where operand order is important. On the other hand, having done only a ...

Updated the M65C02A repository with a new instruction set map. The new instruction set map is for the M65C02B. The M65C02B is a modification of the base instruction set of M65C02A soft-core processor.

The M65C02A has five unused opcodes in Column 2. One of these is reserved for a co-processor, and ...