Hello,

I am new to hardware design and would like to design a 6502 SBC. I am now trying to design a memory mapper/decoder.
The memory layout I came up with is as follows

0000-BFFF = RAM
C000-CFFF = I/O
D000-FFFF = ROM

And the decoder (oututs active low for chip selects)
decoder.PNG
Is that ...

Thank you bogax. Much appreciated.

OK guys, I need your help one more time.
I rewrote my 68.2k routine to check for timeout. This adds 7 cycles to the first wait for start bit loop. And now for the hell of me I can't cycle-up the thing. Please advise :)

Here's the code:

read_from_serial ldx #$3f


wb: ;this is the additional 7 ...

Yes, I always misuse both terms , so I appreciate the pedantic devil in you Thanks.

Hello everyone, just thought I let you know that I managed to get 68,2kbit/s with on the fly checksuming from this sucker :)
Here's the code if anyone's interested. Sekbuf is buffer, count is 0=256bytes $80=128 bytes.


read_from_serial ldx #$3f
lda #0
tay
sta cksum
sta sekbuf-1,y

wb: bit ...

Thanks all again, very insightful tips.

Now, I have, i believe, a clever idea.

Consider only pin 6 changes on portb. and bit7 is 0.
What about this to sample one bit?

Thank you all...

Dr Jefyll: ror @ is accumulator. portb is absolute on non-zero page. your assumptions were ok. The missing cycle is also correct.
Thanks.

BTW, i've managed to do it with branchless approach as BitWise suggested, and used the Alert's tip. It works now for single bytes.
Now I need ...

Thanks for the replies...

Garth: There's no concern about jsr/rts because this does not even happen. I send the bytes through the terminal from the keyboard. One at a time.
So the routine waits for my byte forever, reads it bit by bit when it comes and exits. then again waits for the byte, I send ...

Hi Daryl,

Thanks for reply. Here's the bytes.

sent: 0x41
rcvd: 0x00

sent: 0x42
rcvd: 0x80

sent: 0x44
rcvd: 0x00

sent: 0x48
rcvd: 0x80

Hey,

I'm doing a software serial routines for a 1Mhz 65xx device that needs to communicate at 57600 bit/s. But my receive code does not work.

57600 gives 17 cycles per bit.

Data comes in negated and it comes in on portb's D6. Protocol is
Startbit-Databits-Stopbit (8N1)
#cycle is a macro that ...

Thank you all. Appreciated.

Hey, I'm new here :)

I seem to remember faintly that 6502-like processors had some constrains about the write-sensitive hardware registers. Namely, that write sensitive hardware registers should be decoded with some space between the registers to avoid false writes/reads. Like a page or so. So if ...