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Forum: Programmable Logic Topic: Yet another (unnamed) 65C02 core |
| Windfall |
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Posted: Sun Sep 13, 2020 1:18 pm
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Replies: 40
Views: 16879
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| And yet another 65C02 core was born. Yes, don't look away. :-) Let me first say that making a 6502 core small, efficient, cycle accurate, or any combination thereof, is laudable. I adore efficiency myself. But what about already resource rich environments, like, say, a Stratix V FPGA with nearly a m... |
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Forum: Programmable Logic Topic: Optimizing 6502 core performance in FPGA environments |
| Windfall |
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Posted: Fri May 26, 2017 8:17 pm
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Replies: 18
Views: 4728
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| Okay, the proof of the pudding (referring implicitly to a discussion from the past, started by myself, your mileage may vary ...) : I've always thought (I'm summarizing here) that a 6502 core should not spend such an awful amount of time on fetching instructions. Experimentation time. What did I do ... |
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Forum: Programmable Logic Topic: 32 is the new 8-bit |
| Windfall |
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Posted: Tue Jun 04, 2013 10:49 pm
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Replies: 167
Views: 22344
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| Dear 6502 core writers :D . Say, you can do 32-bit wide memory accesses. Why not exploit this in the core ? Gets rid of all those pesky byte-wide instruction fetches. Instant speedup. E.g. simply replace every opcode fetch with a 32-bit memory read. Combine result with leftover bytes from any previo... |
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Forum: Programmable Logic Topic: Proper 65C02 core |
| Windfall |
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Posted: Sun Apr 22, 2012 9:06 pm
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Replies: 140
Views: 18330
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| Anyone know of a properly working 65C02 core ? Freely available, preferrably Verilog. So far I tried (opencore's) cpu6502_tc and T65 (65C02 mode). Former seemed to work okay, but goes pear shaped on interrupts (took me half a day to find out, and apparently it's a known bug, and has been for two yea... |
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